Abstract: A wafer level stack package according to the present invention has upper and lower semiconductor chips stacked together in a wafer level. Each chip has a first face where bond pads are formed and an opposite second face. The first faces confront each other in a stack. In each chip, metal patterns are connected to the bond pads and intervene between insulating layers. Through holes are formed at both sides of the upper chip, and a pattern film is adhered to the second face of the upper chip. The metal patterns are exposed in the through holes and electrically connected to solder balls on the pattern film. A related method is also provided.

Abstract: A chip-type multi-layered electronic part in which terminal electrodes are prevented from oxidization when the electrical part is joined with a substrate, so that superior electrical bonding between the terminal electrodes and internal electrodes can be attained. Terminal electrodes 7 connected to internal electrodes 1 contain silver and palladium as the main ingredients in the weight ratio in a range of from 7:3 to 3:7, and further contain boron in a range of from 0.1 weight percent to 1.0 weight percent added to the main ingredients of 100 weight percent.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.