Abstract: A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.

Abstract: A stacked multi-chip package is described in which a base die is electrically connected to both an interconnect structure (e.g., a lead frame or a substrate) and a stacked die. A first encapsulant is used to cover some, but not all of the bond pads on a base die as well as portions of their associated electrical connectors (e.g. bonding wires). A surface of the first encapsulant is arranged to support the stacked die. The stacked die is directly electrically connected to bond pads that are not covered by the first encapsulant. A second encapsulant at least partially encapsulates the base and stacked dice and the various electrical connectors. With this arrangement, a stacked multi-chip semiconductor package is provided that includes a direct die-to-die electrical connection.

Abstract: A semiconductor component with an electromagnetic shielding device against alpha radiation, beta radiation and high-frequency electromagnetic radiation is presented. The semiconductor component includes a semiconductor chip with a circuit integrated therein with a number of electrical terminal areas and at least one ground terminal area. The semiconductor also includes a package that contains the semiconductor chip and also a chip carrier. The chip carrier has a number of external electrical terminals and an external ground terminal. The electrical terminal areas and the ground terminal areas of the semiconductor chip are electrically connected to the external electrical terminals and the external ground terminals of the chip carrier by connecting means. The semiconductor chip and the connecting means are in this case encapsulated by an electrically insulating passivation.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: A micromachine package includes a first chip, a second chip, a spacer ring, a plurality of bumps, a plurality of leads, and an encapsulant. The first chip has at least one moveable structure. The second chip has at least one electrode for cooperating with the moveable structure of the first chip, and a plurality of pads disposed on one side of the second chip. The spacer ring is disposed between the first chip and the opposite second chip and surrounds the moveable structure. The bumps are disposed on the pads. The lead has a first surface, which is connected to the bumps, and an opposite second surface. The encapsulant encapsulates the first chip, the second chip, the spacer ring, the bumps, and the first surfaces of the leads, and the second surfaces of the leads are exposed out of the encapsulant.

Abstract: Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.

Abstract: A semiconductor device to prevent breakage of a semiconductor chip is disclosed. The device incorporates a sealing member, a semiconductor chip and having a source and gate electrodes on a first main surface and a drain electrode on a second main surface, a first electrode plate having an upper surface exposed to an upper surface of the sealing member and a lower surface exposed to a lower surface of the sealing member, and second electrode plates each having a lower surface exposed to the lower surface of the sealing member. The drain electrode of the chip is electrically connected to the drain electrode plate through an adhesive. Stud type bump electrodes are formed by gold wire on the source and gate electrodes and are covered with an electrically conductive adhesive. The bump electrode(s) and the source and gate electrode plates are electrically connected with each other through the adhesive.

Abstract: Disclosed is a semiconductor device constructed such that a lead wire extending from an interposer is connected to a pad of a chip, wherein the chip is bonded to a resin molding with a high mechanical strength. In the semiconductor device of the present invention, the lead wires extending from the interposer formed of a polyimide film are connected to the pad of the chip, and the lead wires are arranged sparse. Dummy lead wires irrelevant to the electrical connection are also arranged in addition to the lead wires extending from the interposer so as to increase the total number of lead wires supporting the chip so as to permit the chip 11 to be bonded to the resin molding 15 with a high mechanical strength. The dummy lead wires mounted to the interposer together with the lead wires serve to improve the bonding strength between the resin molding and the chip.

Abstract: A main lead (2) is a single body comprised of an inner lead (2a) and an outer lead (2b) which are integrally formed, the bonding wires are arranged in parallel and fixed onto the inner lead (2a) by the wire bonding portions (3b), and the outer lead are exposed from the mold resin to the outside for electrical connection, and a plurality of through holes (8) penetrating the main terminal lead are formed in the outer vicinity of the wire bonding portions (3b) within the inner lead (2a), and the through holes are arranged substantially in parallel to the arrangement direction of the wire bonding portions (3b) so as to correspond to the entire wire bonding portions (3b).

Abstract: In a semiconductor chip having electrodes formed on the top surface, and electrodes or an insulation layer formed on the back surface, the top-surface electrodes are loop-connected with the back-surface electrodes by wire bonding, or, the top-surface electrodes are connected with the back-surface electrodes or an insulation layer by conductive clip, or by deposited conductive materials. The semiconductor chips thus produced are stacked, and wires, conductive clips, or conductive materials are connected and fixed to each other to produce a stacked semiconductor device in which semiconductor chips of the same size are densely packaged. Thus, a semiconductor device is provided which enables high-density packaging of semiconductor chips even of the same size.

Abstract: An insulating substrate (17) includes a surface conductive layer (25) fixedly laminated on a surface of the plate-like semiconductor body (21) via a surface side fixing member (24, 26). The surface side fixing member (24, 26) includes a first fixing portion (26) for fixing one part (25a) of the surface conductive layer (25) located underneath the joint portion (15) of the electrode terminal (14), and a second fixing portion (24) for fixing the other part (25b) of the surface conductive layer (25) which is not located underneath the joint portion (15), and a fixing strength exhibited by the first fixing portion (26) is smaller than that exhibited by the second fixing portion (24).

Abstract: Support matrices for semiconductors are often encapsulated in a region of the bonding leads, the so-called bonding channel. The encapsulation is effected using a dispensable material that can flow onto the support matrix and causes contamination there. In order to prevent this flow, the support matrix for integrated semiconductors has a frame, conductor track structures and at least one bonding channel. In the bonding channel bonding leads or wires for connecting the conductor track structures to the integrated semiconductor are disposed. Disposed along the edge of the bonding channel a barrier for preventing the flow of flowable material from the bonding channel onto the frame and/or the conductor track structures. A method for producing such support matrices is likewise disclosed.

Abstract: A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.

Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).

Abstract: A semiconductor storage device enables various plural memories to be mounted on the same package, and even though size of respective chips and/or position of bonding pad are different, it is capable of providing a stack MCP in which the chips are superimposed. It causes wiring sheet to intervene between an upper chip and a lower chip. There are provided bonding pads and a wiring pattern for connecting these bonding pads in the wiring sheet. A bonding pad of the upper chip is connected to the bonding pad by a first bonding wire, while the bonding pad is connected to a bonding pad of the package substrate by a second bonding wire. According to this construction, the signal from the upper chip is transmitted to the package substrate via the wiring sheet.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: A method of making semiconductor device packages includes the steps of attaching a wafer to a dielectric layer, testing semiconductor devices in the wafer, and then dicing the layered assembly. The dielectric layer may be, for example, a flexible tape. The semiconductor devices may be chips containing integrated circuits or memory devices. The dicing operation may be performed by a circular saw or by another suitable apparatus. The chips may be connected to input/output devices, such as ball grid arrays, on the dielectric layer, before the testing and dicing steps. Full wafer testing may be-conducted through the ball grid arrays. A relatively stiff metal sheet may be included in the layered assembly before the testing and dicing steps. The metal material may be used as heat spreaders and/or as electrical ground planes. The chips may be connected to the ball grid arrays by wire bonds or flip chip bumps and vias through the dielectric layer.

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract: There is disclosed a TAB style BGA type semiconductor device. This semiconductor device comprises a semiconductor chip on which an integrated circuit is formed, and a polyimide tape which has a conductive pattern and which is allowed to adhere to the semiconductor chip. The conductive pattern includes a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to the outside electrode, and an electrically floating island-like portion in addition to a wiring portion for connecting the bonding portion and the pad portion.