Abstract: A method of translating device layout data to a format for a mask writing tool includes the acts of reading a file defining a number of cells that represent structures on the device. One or more cells are selected and one or more modified cells based on the interaction of the selected cells with other cells in the device layout are created. One or more additional cells is created that will create structures on the mask that are not formed by writing files corresponding to the modified cells and areas that prevent extraneous structures from being formed on the mask at a selected location by the writing of the files corresponding to the modified cells. A jobdeck for the mask writing tool is created that indicates where the files corresponding to modified cells and the one or more additional cells should be written to create one or more masks or reticles.

Abstract: A semiconductor device includes a semiconductor bare chip and an electrically-insulative board member with a thin-film structure capacitor. The semiconductor bare chip has a power supply terminal and a grounding terminal on the back surface thereof. The semiconductor bare chip is mounted on a circuit board by flip-chip bonding. The board member includes a board and a thin-film structure capacitor provided on the board. The capacitor has terminals corresponding to the power supply terminal and the grounding terminal of the semiconductor bare chip thereon. The side of the board member where the capacitor is provided is bonded to the back surface of the semiconductor bare chip. The terminals of the capacitor are electrically connected to the power supply terminal and the grounding terminal of the semiconductor bare chip.

Abstract: Manufacturable processes and the resultant structures utilize metal hydride as an internal source of hydrogen to enhance heat removal within semiconductor packages that employ low dielectric constant materials. The use of a metal hydride heated by internal or external sources facilitates pressurizing hydrogen gas or hydrogen-helium gas mixtures within a hermetically-sealed package. The configuration of the metal hydride can include, where needed to generate the pressure required in larger packages, a relatively large area of metal hydride material on at least one or a plurality of hydrogen generation-dedicated chips. Alternatively, the configuration can include at least one or a plurality of relatively small “islands” of metal hydride material on each of at least one or a plurality of integrated circuit-bearing chips.

Abstract: An electromagnetic matched filter based multiple access communications system having a source of modulated pulses from a digital data stream; an initial filter which shapes the incoming modulated pulse into a desired pulse for transmission across the communication medium; a second filter, identical to the initial filter, which is matched to the pulse which exit the communication medium, a detector which converts the modulated pulse stream into the original digital data stream, and signals which are designed with specific mathematical properties which make the system efficient and minimizes crosstalk between channels. The signals decay rapidly from the central lobe at a higher than 1/x rate and the zero points of the autocorrelation function having high order multiplicities. The type of system allows multiplexing of multiple data streams with much greater flexibility, robustness, and density.

Abstract: A board-shaped thermal conductor base board (3) is arranged on the bottom surface of a power module (1). Substrates (4) and (5) are arranged on the top surface of the thermal conductor base board (3), and semiconductor elements (6) and (7) are respectively arranged on the top surfaces of the substrates (4) and (5). The semiconductor elements (6, 7) are surrounded by a resinous case (2). A source electrode (13) is attached above and apart from the semiconductor elements (6, 7) by using the resinous case (2). The connection between the source electrode (13) and the sources of the semiconductor elements (7) are connected by wire bonding.

Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.

Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

Abstract: A semiconductor device, comprising an electrode on a base surface, a bump formed on the electrode, a pad, and a means of connection. The means of connection comprises a plurality of conductive particles, conducting the bump and the pad with conductive particles bonded between. The base surface is further formed with a barrier rib that separates the conductive particles.

Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.

Abstract: An electronic component and a method for making an electronic component are disclosed. The electronic component has a silicon package. The silicon package has a recess formed thereon in which a conductive region is placed. A bare die electronic device is disposed in the recess. The device has a top, a bottom, sides and a plurality of terminals, including a non-top terminal. The non-top terminal is electrically coupled to the conductive region. The electronic component is constructed by first creating a recess in a silicon wafer to a depth substantially equal to the first dimension of the bare die electronic device. A conductive material is applied to the recess. The electronic device is inserted into the recess so that the bottom terminal is coupled to the conductive material. A dielectric or other planarizing material is applied into the recess. Top and bottom contacts are then applied to form the electronic component so that it may be used as a ball grid array package.

Abstract: A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

Abstract: A wiring board for a semiconductor package comprises a base substrate having first and second surfaces; a wiring layer consisting of necessary wiring patterns formed on at least one of the first and second surfaces; a plurality of semiconductor element mounting areas formed on the surface of the base substrate on which the wiring layer is formed; and individual patterns as position information provided for the respective semiconductor element mounting areas, the individual patterns having a particular shape for the respective semiconductor element mounting area. The individual patterns as position information are formed on peripheral regions of the respective semiconductor element mounting areas.

Abstract: A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.

Abstract: In order to provide a semiconductor device which makes it possible to mount a semiconductor element on the substrate of the semiconductor device main body at the correct position with a higher degree of accuracy, a semiconductor element 2 is mounted at a circuit forming surface of a semiconductor substrate 1 at the periphery of which pad electrodes 5 are provided and a specific area in the semiconductor device containing the semiconductor element 2 is sealed with resin. At the circuit forming surface of the semiconductor substrate 1, reference lines 3 are formed in correspondence to the positions of at least three corners of the semiconductor element 2 to be mounted.

Abstract: An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the series of aligned layers one to another during creation of the integrated circuit. An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface, where the substrate has at least one alignment mark on the second surface.

Abstract: A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant.

Abstract: An integrated circuit package for use in flip-chip manufacturing has a surface having a depression for receiving a bumped die. The depression has disposed on its floor a plurality of cage pads. The depression has four walls, at least one of which is indented to form a step. In the flip-chip manufacturing process, a bumped die is positioned within the depression so that the solder bumps line up with the cage pads, and is precisely aligned and held in place by the depression. The die-package combination is then heated in a furnace to reflow the solder bumps, thus forming an integrated circuit. Using the indentation in the depression, underfill material is introduced into the depression. The underfill material flows into the depression and under the die, surrounding the reflowed solder bumps.

Abstract: A semiconductor device mainly comprises a chip disposed on the upper surface of a substrate. The upper surface of the substrate is provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring. The semiconductor device comprises at least a surface-mountable device connected across the ground ring and the power ring. The semiconductor device of the present invention is characterized by having at least a bonding wire formed across the surface-mountable device. The bonding wire is connected between one of the bonding pads of the chip and the power ring wherein at least one downward depression is formed in a lengthen portion at a top of the bonding wire.

Abstract: A multichip cube structure having a foamed insulating material disposed between adjacent integrated circuit chips. The foamed insulating material has lower dielectric constant and therefore reduces the capacitive coupling between electrical interconnects on adjacent chips. The foamed insulating material also has higher ductility and lower thermal coefficient of expansion than conventional oxide insulators so as to reduce the occurrence of stress induced cracking in circuitry.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.