Abstract: A method of fabricating a semiconductor device including: a first step of forming a through hole in a semiconductor element having electrodes on a first surface; and a second step of forming a conductive layer which is electrically connected to the electrodes and is provided from the first surface through an inner wall of the through hole to a second surface of the semiconductor element which is opposite to the first surface. The conductive layer is formed to have connecting portions on the first and second surfaces so that a distance between at least two electrodes among the electrodes is different from a distance between the connecting portions on at least one of the first and second surfaces, in the second step.

Abstract: Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

Abstract: An access cell for routing current from a first cell to a second cell includes a first current path coupled to a second current path via a third current path. The third current path includes a set of three legs configured in a manner such that a first of the three legs may be severed in half to interrupt current flow between the first current path and the second current path, leaving the other two legs of the third current path intact. Either half of the first leg includes a connection point at which a spare cell may be coupled to the access cell to enable current flow between the spare cell and either the first cell or the second cell.

Abstract: A multiple chip package and method of making the package allow multiple same size or different size chips to be stacked over each other, thereby creating a thin profile multi-chip package. Chips are attached to one surface of a continuous flexible substrate. The substrate has a metallization layer, which is electrically connected to the chips, such as via bond wires attached to center bond pads of the chips and to bond fingers on the metallization layer. Interconnections, such as solder balls, are attached to the other surface of the substrate and only at the portion opposite to the first chip. The substrate is folded to bring the first chip toward a second chip, which are then attached, such as with an insulative adhesive spacer. If any additional chips remain on the substrate, the substrate is folded to sequentially bring each additional chip toward the surface of the substrate opposite to the preceding chip and is secured thereto.

Abstract: To provide excellent reliability and high yield of a semiconductor device that has a multi-wiring structure by using a fluorine-containing silicon oxide film as an interlayer insulating film. A fluorine-containing silicon oxide film is formed so as to cover a lower layer metal wiring. A TEOS film is formed on the fluorine-containing silicon oxide film. After planarizing the TEOS film with the CMP method, an SiH4-based silicon oxide film that is suitable for capturing fluorine is formed on the TEOS film. Metal wirings are formed on the SiH4-based silicon oxide film. A predetermined heat treatment is performed to capture fluorine inside the SiH4-based silicon oxide film. The SiH4-based silicon oxide film is patterned to the same pattern as the metal wirings. After diffusing fluorine into the atmosphere from the exposed area of the TEOS film, a silicon nitride film is formed on the metal wirings.

Abstract: An assembled magnetic body is provided with a ferrite and center electrodes coupled in a different direction from each other to the ferrite, and chip capacitors and a chip resistor are connected between the input/output port of each of the central conductors and a metal case. By forming a hole, in the vicinity of the terminals of the chip components to which input/output ports are connected, in the metal case, the occurrence of a solder ball is prevented and, if a solder ball is caused, the short-circuiting between the terminal electrode of a central conductor and the metal case is prevented.

Abstract: In a motor driving device, an IC chip of a drive circuit for driving a motor is die-bonded to one island of a leadframe, and a diode chip of a protection diode for preventing the drive circuit from being destroyed when supplied power is connected to the IC chip with reverse polarities is die-bonded to another island of the leadframe. The supplied-power pad of the IC chip is wire-bonded to the second island, which serves as the cathode electrode of the diode chip.

Abstract: A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

Abstract: A lead frame for semiconductor device comprising inner leads, outer leads, and dam bars, the inner leads being divided into two groups which are located in opposed areas of the lead frame divided by the center line of the array of the electrode pads of a semiconductor chip to be mounted on the lead frame, and the inner lead having a first end and a second end, the first ends of the respective inner leads being arranged into arrays along an array of electrode pads of the semiconductor chip, so that the array of the first ends has a pitch corresponding to a pitch in the array of the electrode pads, the second ends of the respective inner leads being arranged into arrays at opposed sides of the lead frame, to have a pitch larger than the pitch in the array of the first ends, wherein at least some of the inner leads are arranged to have lengths between the first and the second ends which are substantially equivalent to each other. A semiconductor device using the lead frame is also disclosed.

Abstract: Copper interconnects are formed by depositing substantially pure copper into the lower portion of an interconnect opening. The upper portion of the interconnect opening is then filled with doped copper followed by a planarization process. The resulting copper interconnect exhibits reduced electromigration while maintaining low overall resistivity.

Abstract: In a semiconductor device, a CoSi2 film is interposed between a pluglike contact and a barrier metal film as a silicide film. Consequently, excess reaction can be suppressed on a Ti/polysilicon interface between the pluglike contact or a pluglike local wire and the barrier metal film for stably lowering contact resistance.

Abstract: One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.

Abstract: A heat-spread substrate consisting of a metal heat spreader and a substrate is disclosed. The metal heat spreader has a surface with a cavity, which is adapted for supporting a die. Such surface further includes a ground ring arranged at the periphery of the cavity; a substrate-supporting surface surrounding the periphery of the ground ring; a plurality of first ground pads arranged at the periphery of the substrate-supporting surface; and a plurality of second ground pads arranged on the substrate-supporting surface and protruding it. The substrate is provided on the substrate-supporting surface having a plurality of through holes. The through holes corresponds to the first ground pad so as to make it be located therein, respectively. The substrate further includes a plurality of mounting pads and a plurality of ball pads, in which the mounting pads are close to the cavity, and the first ground pad, the second ground pads and the ball pads are formed in the form of ball grid array and are coplanar roughly.

Abstract: The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.

Abstract: A first semiconductor chip is mounted on a printed circuit board and a second semiconductor chip is mounted on said first semiconductor chip. The second semiconductor chip is displaced in a special direction from the center of the first semiconductor chip. This obviates the need for relay terminals on the side of the first semiconductor chip toward which the second semiconductor chip has been displaced. This allows the first semiconductor chip to be reduced in size by the area that would otherwise be occupied by the relay terminals, and thereby reduces the size of the semiconductor device.

Abstract: A semiconductor device in accordance with the present invention includes a semiconductor element chip pressed and secured on a distortion die-pad so that the semiconductor element chip, sealed inside a package, is held in a predetermined distorted state. The predetermined distorted state is preferably downward or upward warping. The semiconductor element chip operates normally in the distorted state, and does not operate normally when the semiconductor element chip is separated from the semiconductor device, and thereby released from the distortion and laid alone. This ensures that the semiconductor element chip is protected from circuit analysis.

Abstract: A bonding pad structure and a method of fabricating the bonding pad structure allow for a large assembly process margin in the process of connecting a lead to the bonding pad structure. A first insulating layer is formed on a semiconductor substrate. A first conductive layer pattern is formed on a portion of the first insulating layer. The substrate and the first conductive layer pattern are covered with a second insulating layer. A second conductive layer pattern is formed on a portion of the second insulating layer so as to be disposed directly over the first conductive layer pattern. The resultant structure is covered with a third insulating layer. The third insulating layer and the second insulating layer are sequentially patterned to form a via hole through which the top surface of the second conductive layer pattern and a peripheral portion of the first conductive layer pattern are exposed.

Abstract: A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages that are arranged to have relatively low inductance are disclosed. In one aspect, a leadless semiconductor package is described having an exposed die pad and a plurality of exposed contacts that are formed from a common substrate material. The die attach pad, however, is thinned relative to at least a portion of the contacts. A die is mounted on the thinned die attach pad and wire bonded to the contacts. Since the die attach pad is lower than the contact surface being wire bonded to, the length of the bonding wires can be relatively reduced, thereby reducing inductance of the device. A plastic cap is molded over the die and the contacts thereby encapsulating the bonding wires while leaving the bottom surface of the contacts exposed. In some embodiments, the die is arranged to overhangs beyond the die attach pad towards the contacts.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulting films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: A semiconductor device mainly comprises a chip disposed on the upper surface of a substrate. The upper surface of the substrate is provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring. The semiconductor device comprises at least a surface-mountable device connected across the ground ring and the power ring. The semiconductor device of the present invention is characterized by having at least a bonding wire formed across the surface-mountable device. The bonding wire is connected between one of the bonding pads of the chip and the power ring wherein at least one downward depression is formed in a lengthen portion at a top of the bonding wire.