Abstract: Disclosed is a method for manufacturing a semiconductor wafer having an epitxial layer on a surface thereof, by the steps of forming a pritective oxide film on a surface of a semiconductor wafer prior to loading of the wafer into an eptaxial growth furnace, removing the protective oxide film formed on the surface of the wafer by heating after the wafer is loaded in the furnace, and performing epitaxial growth of the epitaxial layer on the surface from which the protective oxide film is removed in the furnace. The protective oxide film is removed by heating the wafer in the furnace in an ambience of hydrogen gas at a pressure ranging from 0.0133×105 Pa to 1.013×105 Pa and at a temperature ranging from 800° C. to 1,000 ° C., or by heating the wafer in the furnace at a pressure of 5×106 Pa or under and at a temperature ranging from 800° C. to 1,000° C.

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (12) in which impurity is diffused is deposited on the entire surface including the inside of a hole (8A). An etching process of the polysilicon layer (12) is performed to form a storage node electrode composed of the polysilicon layer (12) remaining on the bottom and side of a groove for metallization (15) and in the hole (8A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (15), and a plug part disposed in the hole (8A). The storage node electrode is electrically connected via the plug part to a diffused region (19) of a semiconductor substrate (1).

Abstract: Source/drain regions of an MOS transistor are formed at a surface of a p-type silicon substrate. A storage node electrically connected to the source/drain regions penetrates a bit line to reach the n-type source/drain region. The storage node and the bit line are insulated from each other by a sidewall insulating layer. Thus, a semiconductor memory device suitable for high integration is obtained in which short-circuit between the storage node and the bit line on a gate electrode layer can be prevented.

Abstract: The present invention is directed to a method of forming an insulative layer over a fuse link in a semiconductor device that is sufficiently thick to encapsulate the fuse link during laser opening, thereby preventing vaporized metal from re-depositing on the fuse link. The layer is also sufficiently thin to allow the laser to penetrate the insulative layer during laser opening of the fuse. A primary dielectric layer is formed over a metal fuse link, the primary dielectric having a predetermined deposition thickness over the fuse link. The primary dielectric layer is then covered with an etch interrupting layer. The etch interrupting layer is covered with a secondary dielectric layer and a portion of the secondary dielectric layer is then removed, resulting in an interlayer dielectric (ILD) stack formed from the etch interrupting layer and the remaining secondary dielectric layer. The ILD has a selected thickness that is greater than the thickness of the primary dielectric layer.

Abstract: The present invention addresses a problem associated with exposing a photoresist layer of non-uniform thickness. Oftentimes, trench patterns etched into a layer of a semiconductor structure will have trenches of varying sizes. Larger trenches in the structure become filled with photoresist material, while smaller trenches do not leading to non-uniformity of photoresist layer thickness with respect to the large and small trenches. The present invention addresses this non-uniformity in photoresist layer thickness by employing at least two exposure steps when exposing the photoresist layer. A first exposure step exposes portions of the photoresist layer corresponding to the large trenches using a first reticle and first energy level. Next, a second exposure step exposes portions of the photoresist layer corresponding to the small trenches using a second reticle and second energy level.

Abstract: An anti-fuse for programming a redundancy cell and a repair circuit having a programming apparatus are disclosed.

Abstract: A conductive metal oxide based layer on a substrate is prepared by chemically reducing a metal salt in aqueous solution, coating the resulting aqueous metal dispersion after washing onto a substrate, preferably glass, and subjecting the coated layer to an oxidizing treatment, e.g. a heat step. In a preferred embodiment the metal oxide is tin oxide, or a mixture of tin oxide and another metal oxide.

Abstract: A method for fabricating a borderless contact is disclosed. The method includes providing a substrate with an active region and a trench formed therein. Then, the trench is etched to stop at a depth. A conformal stop layer is deposited on the substrate. As a key step, the stop layer is etched to form spacer against top corner of the trench. A dielectric layer is formed on the substrate. Then, an opening is etched in the dielectric layer to form a borderless contact, wherein the opening overlies both a portion of the trench and a portion of the active region.

Abstract: A method of fabricating a dummy pattern is proposed. A semiconductor substrate is divided into a dense region and a sparse region. Conducting patterns are formed on the dense region. A dielectric layer is formed over the substrate and the conducting patterns. Photoresist patterns are formed on the dielectric layer above the sparse region. The dielectric layer is etched back to form a plurality of spacers on the sidewall of the conducting patterns, and simultaneously, a plurality of dummy patterns are formed on the sparse region.

Abstract: A method of forming a fluorinated silicon oxide layer or an FSG film having a dielectric constant less than 3.2 is disclosed. The method includes introducing a fluorine-rich gas into a reacting chamber, introducing an oxygen-rich gas into the reacting chamber, creating a plasma environment in the reacting chamber to deposit the FSG film, and adjusting the flow rate of the oxygen-rich gas till the ratio of the flow rate of the oxygen-rich gas to the total flow rate of the fluorine-rich gas and silicon-rich gas is less than or equal to a pre-selected value to form the FSG film. The refraction index (RI) of the fluorinated silicon oxide layer must be greater than or equal to 1.46.

Abstract: A plasma processing method comprising the steps of arranging a substrate on a film is to be formed in a reaction chamber capable of being vacuumed and evacuating the inside of the reaction chamber in a loading stage; and separating the reaction chamber from the loading stage and joining the reaction chamber to a treating stage where the substrate arranged in the reaction chamber is subjected to plasma processing, wherein the reaction chamber is moved on a track to join to the treating stage, where a high frequency power supply system, a processing gas supply system and an exhaustion system are joined to the reaction chamber, whereby plasma is produced in the reaction chamber to conduct plasma processing on the substrate. An apparatus suitable for practicing said plasma processing method.

Abstract: A method of fabricating a thin film transistor includes crystallizing an amorphous silicon layer having a sloping surface and a flat surface by an SLS technique using a laser beam having predetermined energy density so as to melt the sloping surface as well as the flat surface of the amorphous silicon layer to form a crystallized silicon layer and forming the active layer by selectively etching the crystallized silicon layer. The laser beam is applied non-vertically to the sloping surface while the laser beam is applied vertically to the flat surface. Although the sloping surface and the flat surface of the amorphous silicon layer are irradiated with a laser beam having the same laser energy density, the absorbed energy density of the sloping surface may be lower than that of the flat surface. The laser beam generates a first energy density to substantially melt the sloping surface and a second energy density to substantially melt the flat surface of the amorphous silicon.

Abstract: A formed SiC product having a low degree of light transmittance useful in a variety of heat resistant components such as equalizing rings, dummy wafers, and other components employed in semiconductor manufacturing facilities, and the manufacturing method thereof. The product is a CVD-formed SiC product prepared by growing a coating on a substrate with a CVD process and thereafter removing the substrate. The product is characterized by having at least one SiC layer with different grain characteristics located either on its surface or within the main structure, and having a light transmittance rate of 0.4% or less for the wavelength range from 300 to 2,500 nm, and 2.5% or less for the wavelength range exceeding 2,500 nm. The method for manufacturing the formed SiC product is characterized by forming at least one SiC layer with different grain characteristics either on its surface or within the main structure provided by changing the CVD reaction conditions.

Abstract: The invention relates to a semiconductor process, and in particular to a method and structure of manufacturing contact windows between different levels of two conductive layers (a upper conductive layer and a lower conductive layer) in the semiconductor process. In the method, first, a trench is formed under a subsequently-formed contact window between the upper conductive layer and lower conductive layer. The trench may be located on the insulating layer under the lower conductive layer. When the lower conductive layer is subsequently formed, the trench can be filled with the lower conductive layer. Therefore, part of the lower conductive layer on the trench is thicker than that on the other regions. When the insulating layer between the upper conductive layer and lower conductive layer is formed, an etching process is then performed to form the contact window, the contact window can not cross the lower conductive layer due to the lower conductive layer on the trench being sufficiently thick.

Abstract: In a method is described for producing an MOS transistor structure with elevated body conductivity, a substrate layer is prepared and body regions are formed therein the body regions defining a main surface of the transistor structure and at least one channel region is also formed. Gate oxide and gate electrodes are formed in the region of the main surface, and source regions are formed that extend from the main surface into the body regions. An implantation of dopant of a first conductivity type occurs in at least a part of the channel region, this implantation dosage being controlled such that a re-doping of the body region into an area of the first conductivity type does not occur in the implantation region.

Abstract: The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor.

Abstract: The formation of an adhesion/interlayer region (410) of a semiconductor substrate device (404) before barrier layer (412) deposition provides improved adhesion of the barrier layer (412) to the underlying dielectric (404) and increases strength to the next interconnect layer without altering the function of the barrier layer (412) to limit Cu diffusion into the dielectric substrate (404). The adhesion/interlayer region (410) is formed in an inlaid structure (400, 500) of a semiconductor wafer. The inlaid structure (400, 500) is connected to upper or lower metal layers through vias in the dielectric layer (404) to a copper layer. The adhesion/interlayer region is formed by flowing a treating gas in a glow discharge process of the dielectric substrate in a chamber either attached or separated from the barrier deposition chamber (300). The barrier layer (412) and the adhesion/interlayer region (410) can be formed in this inlaid structure (400, 500) of a semiconductor wafer.

Abstract: To efficiently remove catalytic elements from a crystalline semiconductor film. An Ni film is formed so as to come in contact with a semiconductor thin film of low crystallinity made of an amorphous silicon film, a microcrystalline silicon film or the like. The semiconductor thin film 12 of low crystallinity is heated at 450 to 650° C. to form a crystalline semiconductor thin film in which Ni is diffused. The film is again heated at 500 to 1,100° C. to crystallize amorphous components remained in the semiconductor film to form a crystalline semiconductor film of enhanced crystallinity. Next, the crystalline semiconductor film is irradiated with a laser light or an intense light to have easily diffused Ni that is locally present in the semiconductor film in a form of silicide. Catalytic elements are then selectively added in the crystalline semiconductor film to form XV-element added regions. Subsequently, heating at 500 to 850° C.

Abstract: The invention relates to a method of manufacturing an integrated semiconductor device on a substrate (1), comprising steps to manufacture a stack of layers (2, 3, 4, 5) on the substrate, and steps to manufacture circuit elements by means of photolithography including the formation of a centering mask, the formation of a reference pattern through an opening in this mask, and the formation of masks for defining circuit elements centered on the reference pattern.

Abstract: A buried hetero-structure with native oxidized current blocking layer for InP-based opto-electronic devices comprises a InP semiconductor substrate, a buffer layer, a ridge mesa containing lower confinement layer, active layer and upper grating confinement layer, a first InP cladding layer and a native oxidized Al-bearing layer as current blocking layers at both lateral edges, a second InP cladding layer, contact layer, contact metal, and the second ridge mesa covered with insulating layer. This method is to facilitate the processing of conventional buried hetero-structure InP-based opto-electronic device and improve the performance under high temperature and high current operation.