Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate a exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.

Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Abstract: The semiconductor region of an intrinsic collector is surrounded with a lateral insulating region. A semi-conducting layer comprising a SiGe heterojunction is partially located between the transmitter and the intrinsic collector and extends on either side of the transmitter above the lateral insulating region. The base intrinsic region is formed in said semi-conducting layer with heterojunction between the transmitter and the intrinsic collector. The base extrinsic region and the collector extrinsic region respectively comprise first zones formed in said semi-conducting layer with heterojunction, located respectively on either side of the transmitter and above the lateral insulating region first part and mutually electrically insulated by the lateral insulating region second part.

Abstract: A stacked integrated circuit structure, in which main package bodies of a plurality of integrated circuits are stacked on each other. Connections between leads of the stacked integrated circuits are made by means of a stacking substrate. Therein, each of two surfaces of the stacking substrate has a plurality of terminals electrically connected to corresponding terminals. The stacking substrate includes a plurality of through vias as well, which connect to the corresponding terminals of the two surfaces. For two stacked integrated circuits, a hole can be defined in the stacking substrate, which housed the main package body of one of the two stacked integrated circuits, or by means of a plurality of separated substrates arranged around the perimeter of the main package body of one of the two stacked integrated circuits, so that the thickness of the stacked integrated circuits can be reduced.

Abstract: A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.

Abstract: A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to further increase the surface area of the electrode.

Abstract: An apparatus for processing semiconductor wafers includes a single imaging stepper for exposing wafers processed on a first track and a second track. A method for processing semiconductor wafers includes selecting one of a first coater and a second coater for coating a first wafer with a photoresist. The coated wafer is exposed in a single stepper to form an exposed wafer. An operator selects one of a first developer and second developer to develop the exposed wafer.

Abstract: A silicon carbide film is formed in a manner which avoids the high level contents of oxygen by depositing the film in at least two consecutive in-situ steps. Each step comprises plasma enhanced chemical vapor deposition (PECVD) of silicon carbride and ammonia plasma treatment to remove oxygen contained in the deposit silicon carbide. The disclosed method is found to enhance several insulation properties of the silicon carbide film and can be easily adapted into production-level IC processing.

Abstract: A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

Abstract: A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors.

Abstract: A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.

Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.

Abstract: A semiconductor memory device, a method for manufacturing the same, a memory circuit including the semiconductor memory device, and a method for driving the same, are provided. In detail, one transistor forms a memory cell, and a single transistor cell capable of arbitrarily accessing the memory cell, a method for manufacturing the same, a memory circuit, and a method for driving the memory circuit, are provided. An island type semiconductor layer as an active region is formed on a ferroelectric layer. A word line crosses the semiconductor layer. A source is formed on the semiconductor layer on one side of the word line, and a drain is formed on the other side. A plate line is formed below the ferroelectric layer to face the word line, and intersects the word line. A drive line is connected to the source, and a bit line is connected to the drain.

Abstract: A method of manufacturing an SOI (silicon on insulator) wafer includes the step of selective anisotropic etching to form, in the substrate, trenches which extend to a predetermined depth from a major surface of the substrate and between which pillar portions of the substrate are defined. The method further includes the step of selective isotropic etching to enlarge the trenches, starting at a predetermined distance from the major surface, thus reducing the thicknesses of the pillar portions of the substrate between adjacent trenches. Also, the method includes the steps of selective oxidation to convert the pillar portions of reduced thickness of the substrate into silicon dioxide and to fill the trenches with silicon dioxide, starting substantially from the predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate.

Abstract: A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon connected to the integrated circuitry. At least one electrically conductive wire bond is made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads, which are not interconnected via the integrated circuitry within the die. The first bond pad can be a lead finger on the active surface and the second bond pad can be an option bond pad electrically connected to a third bond pad selected from the plurality of bond pads on the active surface via the integrated circuitry. Further, the third bond pad can connect to a fourth bond pad selected from the plurality of bond pads via a wire bond. The first bond pad can also be an internal voltage line and the second bond pad an external voltage line or the bond pads can be different internal buses within the integrated circuitry.

Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.

Abstract: A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press.

Abstract: A semiconductor light emitting device has a light emitting layer forming portion formed on the substrate and having an n-type layer and a p-type layer to provide a light emitting layer. A window layer is formed on a surface side of the light emitting layer forming portion. The window layer is formed of AlyGal−yAs (0.6≦y≦0.8) auto-doped in a carrier concentration of 5×1018-3×1019 cm−3. The resulting semiconductor light emitting device is free of degradation in crystallinity due to p-type impurity doping, thereby provide a high light emitting efficiency and brightness without encountering device degradation or damage.

Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. An oxidation of the substrate is performed to provide for round corners at a perimeter of the trench area. The substrate is then etched to form a trench within the trench area.

Abstract: A process for fabricating a semiconductor device comprising the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.