Patents Examined by Christian D. Wilson
  • Semiconductor pressure sensor device having sensor chip covered with protective member
    Patent number: 6512255
    Abstract: A sensor device has a semiconductor sensor chip mounted on a resin package with which insert pins are insert-molded. The sensor chip and the pins are electrically connected to each other by bonding wires. An electrically insulating protective member covers the chip, the pins, and the wires. The protective member has a saturated swelling coefficient of approximately 7 wt % at most when the protective member is immersed into gasoline having a temperature of 20° C. Accordingly, bubbles are prevented from being produced in the protective member.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: January 28, 2003
    Assignee: Denso Corporation
    Inventors: Takashi Aoki, Yoshifumi Watanabe, Takashi Nomura
  • Metal gate stack with etch stop layer
    Patent number: 6511911
    Abstract: A metal gate structure and method of forming the same employs an etch stop layer between a first metal layer, made of TiN, for example, and the metal gate formed of tungsten. The etch stop layer prevents overetching of the TiN during the etching of the tungsten in the formation of the metal gate. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum in the etch stop layer allows a thin etch stop layer to be used that provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: January 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Srikanteswara Dakshina-Murthy
  • Method of making trench-gated MOSFET having cesium gate oxide layer
    Patent number: 6509233
    Abstract: Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: January 21, 2003
    Assignee: Siliconix incorporated
    Inventors: Mike Chang, Sik Lui, Sung-Shan Tai
  • Conductive device components of different base widths formed from a common conductive layer
    Patent number: 6509626
    Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: January 21, 2003
    Inventor: Alan R. Reinberg
  • Process for manufacturing electronic devices comprising nonvolatile memory cells of reduced dimensions
    Patent number: 6509222
    Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: January 21, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Grossi, Cesare Clementi
  • Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
    Patent number: 6507096
    Abstract: A tape having implantable conductive lands, which realizes a new structure in which an organic rigid substrate is removed from a semiconductor package in a semiconductor packaging process, and a method for manufacturing the tape are provided. The tape includes a tape film, which can be detached from a semiconductor package after an encapsulation process and serves as a general rigid substrate until the encapsulation process is completed, and implantable conductive lands adhering to the tape film.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: January 14, 2003
    Assignee: Kostat Semiconductor Co., Ltd.
    Inventor: Heung-su Gang
  • Printed circuit board with integral heat sink for semiconductor package
    Patent number: 6507102
    Abstract: A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: January 14, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Frank J. Juskey, John R. McMillan, Ronald P. Huemoeller
  • Fuse configuration for a semiconductor apparatus
    Patent number: 6501150
    Abstract: A fuse configuration for a semiconductor apparatus is described. The fuse configuration has a semiconductor material disposed underneath the fuse and is made porous by implantation and subsequent etching, so that it provides a thermal insulation. The thermal insulation protects the semiconductor body when the fuse is blown due to a decreased energy requirement for blowing the fuse.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: December 31, 2002
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Welser
  • SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
    Patent number: 6498370
    Abstract: A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: December 24, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wug Kim, Byung-Sun Kim, Hee-Sung Kang, Young-Gun Ko, Sung-Bae Park
  • Laser processing method
    Patent number: 6495404
    Abstract: A laser processing apparatus provides a heating chamber, a chamber for laser light irradiation and a robot arm, wherein a temperature of a substrate on which a silicon film to be irradiated with laser light is formed is heated to 450 to 750° C. in the heating chamber followed by irradiating the silicon film with laser light so that a silicon film having a single crystal or a silicon film that can be regarded as the single crystal can be obtained.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: December 17, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Teramoto, Hisashi Ohtani, Akiharu Miyanaga, Toshiji Hamatani, Shunpei Yamazaki
  • Removing inherent stress via high temperature annealing
    Patent number: 6489184
    Abstract: Methods and apparatus are provided which decrease the amount of movement likely to occur during processing of a substrate. In particular, a horizontally supported dielectric panel is subjected to a series of processing steps during which the panel is heated, cooled, or maintained at a fixed temperature so as to a achieve a 2 to 1 reduction in material movement during subsequent processing. It is contemplated that application of the disclosed methods to a dielectric panel will be particularly beneficial when application is accomplished prior to laser drilling and sputtering the panel.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: December 3, 2002
    Assignee: Honeywell International Inc.
    Inventors: Richard Pommer, Glen Roeters, Jim Yardley
  • Method of manufacturing a TFT with Ge seeded amorphous Si layer
    Patent number: 6482684
    Abstract: There is provided a semiconductor device using a semiconductor thin film having high crystallinity, which is formed by a manufacturing method with high productivity. When active layers of an amorphous silicon film are crystallized, germanium is used as a catalytic element for facilitating crystallization. When a heat treatment is carried out in a state where the active layers are in contact with a germanium film through an opening portion provided in a mask insulating film, the active layers made of a polysilicon film are obtained by crystal growth in a lateral direction.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: November 19, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Laser processing method
    Patent number: 6482687
    Abstract: A laser processing apparatus provides a heating chamber, a chamber for laser light irradiation and a robot arm, wherein a temperature of a substrate on which a silicon film to be irradiated with laser light is formed is heated to 450 to 750° C. in the heating chamber followed by irradiating the silicon film with laser light so that a silicon film having a single crystal or a silicon film that can be regarded as the single crystal can be obtained.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: November 19, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Teramoto, Hisashi Ohtani, Akiharu Miyanaga, Toshiji Hamatani, Shunpei Yamazaki
  • Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate
    Patent number: 6482688
    Abstract: A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Chimin Hu, Amitabh Jain, Reima Tapani Laaksonen, Manoj Mehrotra
  • Failure analysis method for chip of ball grid array type semiconductor device
    Patent number: 6472234
    Abstract: In a failure analysis method for a ball grid array type semiconductor device including a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the second solder balls and the interposer substrate are removed from the semiconductor device, and then, the first solder balls are removed from the semiconductor device. Then, the semiconductor device is mounted on a package, and a wire bonding operation is performed between the pads of the semiconductor chip and bonding pads of the package. Finally, a test operation is performed upon the semiconductor chip by mounting the package on a tester.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: October 29, 2002
    Assignee: NEC Corporation
    Inventor: Tadashi Ozawa
  • Method for forming a spacer for semiconductor manufacture
    Patent number: 6472280
    Abstract: Methods for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a LDD structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention includes a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention includes a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: October 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Nanseng Jeng, Christophe Pierrat
  • Ferroelectric capacitor with a self-aligned diffusion barrier
    Patent number: 6462368
    Abstract: A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layer of a switching transistor is self-aligned. As a result, side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: October 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyoshi Torii, Yasuhiro Shimamoto, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki
  • Indium-enhanced bipolar transistor
    Patent number: 6459140
    Abstract: A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price of high beta and high base resistance, separate boron and indium doping profiles are combined in the base. Thus, a transistor, which preserves most of the properties of pure boron-base transistor, is obtained, but with some parameters improved due to the added indium profile. This “double-profile” or “indium-enhanced” transistor exhibits improved beta-Early voltage product, reduced collector-base capacitance swing and lower temperature dependence of beta, but preserves the advantageous properties of a pure boron-base transistor.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: October 1, 2002
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Ted Johansson, Hans Norström
  • Semiconductor device, method of manufacturing the same and method of arranging dummy region
    Patent number: 6455894
    Abstract: Provided are a semiconductor device capable of satisfactorily solving a floating-body problem and a hot carrier problem which often arise in an SOI device and of causing a widely distributed partial isolating film to generate a crystal defect for peripheral structures with difficulty and a method of manufacturing the semiconductor device. A dummy region DM1 having no function as an element is formed at almost regular intervals in a partial isolating film 5b provided between MOS transistors TR1. Consequently, the occupation rate of the dummy region DM1 having a lower resistance value than that of a silicon layer 3b provided under the partial isolating film 5b is increased so that the floating-body problem and the hot carrier problem can be solved.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: September 24, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
  • Method and apparatus for filling a gap between spaced layers of a semiconductor
    Patent number: 6455349
    Abstract: A semiconductor device assembly with a gap to be filled has thermal vias formed in the supporting substrate. After the semiconductor device is connected to the substrate and fill material positioned about the gap to create a seal, a vacuum is drawn through the thermal vias and a pressure applied to the fill material to urge the fill material into the interior of the gap.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: September 24, 2002
    Assignee: Micron Technology, Inc.
    Inventor: J. Michael Brand