Abstract: A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.

Abstract: A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Abstract: An improved flash memory device, which comprises core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer, and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device.

Abstract: A process for producing a large number of semiconductor chips from a semiconductor wafer having a large number of rectangular areas defined by streets arranged on the front surface in a lattice form, semiconductor circuits being formed in the respective rectangular areas. This process comprises the steps of forming a plurality of grooves having a predetermined depth in the back surface of the semiconductor wafer, grinding the back surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer to a predetermined value and thereafter, cutting the semiconductor wafer along the streets to separate the rectangular areas from one another to obtain semiconductor chips.

Abstract: A device includes a silicon substrate provided with a coating including at least one stacking constituted by a plane of GaN or GaInN quantum dots emitting visible light at room temperature in a respective layer of AIN or GaN. The method of making the device is also disclosed. The device can be incorporated in electroluminescent devices and exchange devices, emitting white light in particular.

Abstract: A thin film resistor element which maintains its resistance value when stress is applied such as during packaging, so that the resistor element may be used in a high precision bleeder resistor circuit to maintain an accurate voltage dividing ratio. The thin film resistor element has a P-type thin film resistor formed of a P-type semiconductor thin film and an N-type thin film resistor formed of an N-type semiconductor thin film, so that a change in resistance value when stress is applied is prevented. In a bleeder resistor circuit, a resistance value of one unit is regulated by a resistance value formed by a combination of the P-type thin film resistor and the N-type thin film resistor so that, even in the case where stress is applied, a change in resistance values of the respective resistor elements cancel out each other and an accurate voltage dividing ratio can be maintained.

Abstract: A split gate electrode MOS FET device includes a tunnel oxide layer formed over a semiconductor substrate. Over the tunnel oxide layer, a doped first polysilicon layer is formed with a top surface. A native oxide which forms over the doped first polysilicon layer may have been removed as an option. On the top surface of the first polysilicon layer, a silicon nitride layer was etched to form it into a cell-defining layer. A polysilicon oxide dielectric cap was formed over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, the first polysilicon layer and the tunnel oxide layer were formed into a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Spacers are formed on the sidewalls of the gate electrode stack. Blanket inter-polysilicon dielectric and blanket control gate layers cover exposed portions of the substrate and the stack.

Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.

Abstract: A wire bonding method comprising: disposing a plurality of leads (20) aligned in an imaginary plane (P) around the periphery of a semiconductor chip (10) having a plurality of electrodes (12) aligned on an imaginary straight line (L1); bonding wires (30) to the electrodes (12); bending the wires (30) toward the leads (20) as viewed from a direction perpendicular to the imaginary plane (P); and bonding the wires (30) to the leads (20).

Abstract: A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench.

Abstract: The cell density of power MOSFET used as a switch is determined by the width of the trench formed in the device, the processing limit of which is limited by the spatial resolution of the exposure apparatus used in the photolithographic process. This invention provides a method of manufacturing such devices which overcomes the processing limitation imposed by the exposure apparatus, and doubles the cell density and reduces the input capacitance for further reducing the on-state resistance and improving the switching speed. By forming a second CVD oxide film over a first oxide film defining the opening for forming a trench and subsequent anisotropic RIE etching of the second film, a side-wall film is added to the mask pattern, which promotes a further reduction of the width of the trench by more than one half.

Abstract: In a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode which is in the form of a cylinder having an open top and a closed bottom, an upper end of a partition, which is formed of an insulating material between adjacent cylindrical lower electrodes, has an sharpened tip end and an inclined surface descending from the sharpened tip end toward each adjacent cylindrical lower electrode. With this arrangement, it is possible to prevent silicon grains of a hemi-spherical grain silicon from nidating on the partition, thereby prevent a short-circuiting between the adjacent cylindrical lower electrodes, without reducing the capacitance of the memory cell.

Abstract: The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.

Abstract: A high inductance and high-Q inductor structure formed using multilevel interconnect technology with deep trench has the same current flow direction in each spiral coil pattern. The inductor uses reflection and rotation transformation to generate each spiral coil pattern and neighboring spiral coil pattern relatively rotates with respect to the lower spiral coil pattern. Each spiral coil connection follows the connection code of edge end to edge end and central end to central end through via plugs. Each spiral coil is connected in series and total inductance results from summation of each spiral coil pattern.

Abstract: The present invention relates to a non-volatile semiconductor memory device, having the higher margin of the implanted ion passing through a source-to-drain electrode, as well as the excellent covering power of an embedded layer deposited in and above a groove within a field oxide region distributed at both the source-to-drain electrode and a source area. The present invention also provides a method for manufacturing the non-volatile semiconductor memory device.

Abstract: The invention relates to a solid-state imaging device (1) which is encapsulated in a ceramic package covered by a transparent window (6) comprising a phosphorus-containing glass. The window is provided with a coating (8), for example of chromium, at the circumference of the window to counteract degradation of the joint between the window and the ceramic package, which degradation results from the sensitivity of phosphorus glass to moisture. The use of phosphorus glass has the advantage that it is opaque to infrared radiation, so that the application of a separate coating serving as an IR filter is avoided and hence the dependence of the sensitivity of the imaging device on the angle of incidence of the radiation to be detected.

Abstract: Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.

Abstract: A new method is provided for the creation of a pre-molded chip carrier. The invention teaches putting magnetic inserts into the upper mold. The magnetic inserts attract the lead fingers that are inserted into the upper mold during the process of filling the cavity with a compound pressing the lead fingers tightly against the surface of the magnet. The possibility of mold compound spilling over the lead fingers and forming resin depositions on the surface of the lead fingers is thereby voided.

Abstract: A variety of techniques for electrically debussing conductive substrate panels used in the formation of a matrix of leadless integrated circuit packages are described. Generally, after a matrix of leadless packages have been fabricated in panel form on a conductive substrate panel, tie bars that are used to support contacts and potentially other structures on the conductive substrate are removed after plastic caps have been molded over the matrix, but before separating the packaged devices. This serves to electrically isolate the contacts from one another while leaving sufficient portions of the molded substrate structure in tact to facilitate handling the structure in panel form. With the described arrangement, the packaged devices may be tested in panel form. After testing and any other desired panel based operations, the packaged devices may be separated using conventional techniques. The removal of the tie bars can be accomplished by any suitable technique including, for example, sawing or etching.

Abstract: A process to selectively form silicon structures, such as a storage capacitor, by forming a conductive silicon, forming a silicon nitride layer on the conductive silicon substrate, forming a tungsten layer on the silicon nitride layer, patterning the tungsten layer and the silicon nitride layer to expose a underlying portion of the conductive silicon substrate, forming a continuous silicon film on the exposed portion of the conductive silicon substrate and on an adjacent portion of the silicon nitride layer while completely converting the tungsten layer to a tungsten silicide film by presenting a silicon source gas to the semiconductor memory assembly to form a continuous conductive silicon film used as a first capacitor electrode, forming a capacitor dielectric on the first capacitor electrode and the oxide layer, and forming a second capacitor electrode on the capacitor dielectric.