Abstract: Described is a method to form isolation structures on a semiconductor substrate. This method begins with forming one or more trenches in the semiconductor substrate and depositing a first portion of a dielectric layer at a first rate by a High Density Plasma—Chemical Vapor Deposition into the trenches and onto the semiconductor substrate. This first deposition at least partially fills the trenches and may completely fill the trenches. Next, a second portion of the dielectric layer is deposited at a second rate by the High Density Plasma—Chemical Vapor Deposition over the semiconductor substrate to partially planarize the dielectric layer. This second deposition is preferably performed with a different flow rate of reaction gasses than the first deposition. Finally, a portion of the dielectric layer that was deposited at the second rate is removed by a CMP process, for example.

Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Abstract: A semiconductor device formed of a first dummy interconnect, an interlayer insulating film and a second dummy interconnect which are formed on a semiconductor chip in this order and a plurality of dummy via holes formed in the interlayer insulating film between the first dummy interconnect and the second dummy interconnect; wherein at least one of the first dummy interconnect and the second dummy interconnect is connected with at least two of the dummy via holes.

Abstract: A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: An organic substrate and a heat spreader are separately made, and are then combined with a partially cured liquid-type adhesive layer. In making the organic substrate, a solder mask and a cavity as a pocket for an IC die are first formed on one side of an organic substrate. A pre-treatment process is performed to a copper layer on the opposite side of the organic substrate. A black ink layer is layered on one side of the heat spreader, and a second black ink layer is formed within a predetermined area on its opposite side. The predetermined area is reserved for positioning the IC die, and has a plurality of heat dissipating pads. A liquid-type adhesive printing process and a partial curing process are performed, which forms a solidified liquid-type adhesive layer outside of the predetermined area. The organic substrate is then laminated to the Cu heat spreader under high temperatures. Finally, a Ni/Au layer is plated onto a plurality of conductive pads and heat dissipating pads of the substrate.

Abstract: The specification describes a dual level gate for reducing hot carrier effects in MOS transistors. The dual level gate is formed by undercutting the edges of the gate using a wet etch, and growing oxide in the undercut to a thickness exceeding the gate oxide thickness, thereby lifting the edge of the gate and reducing the electric field concentration at the drain edge of the gate.

Abstract: A process of manufacturing a semiconductor device having a dual gate CMOS transistor in which an nMOS transistor in the dual gate CMOS transistor is formed by the steps of: (a) forming a gate insulating film and a silicon film on a semiconductor substrate; (b) implanting n-type impurities into the silicon film in an nMOS region of the semiconductor substrate; (c) forming a conductive film on the silicon film; and (d) patterning the silicon film and the conductive film into a gate electrode.

Abstract: A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (16a, 16b, 20a, and 20b) between these layers (16 and 20) and their adjacent dielectric layers (18 and 22) are positioned in the stack (13) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (13). Etch processing is then used to position the layers (16) and (20) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

Abstract: A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by forming a relatively thick silicon oxide liner on the side surfaces of the gate electrode and adjacent surface of the semiconductor substrate before forming the silicon nitride sidewall spacers thereon. Embodiments include forming a silicon dioxide liner at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers thereon.

Abstract: An object of the present invention is to provide a TFT with which better characteristics can be obtained using a good crystalline silicon film. An amorphous semiconductor film having a thickness of 400 Å or more is formed on an insulating surface, is crystallized by heat annealing or photo annealing or the combined use thereof, and is wholly or selectively etched to form a region having a thickness of 300 Å or less. This is used as a channel-forming region in a TFT.

Abstract: A tape having implantable conductive lands, which realizes a new structure in which an organic rigid substrate is removed from a semiconductor package in a semiconductor packaging process, and a method for manufacturing the tape are provided. The tape includes a tape film, which can be detached from a semiconductor package after an encapsulation process and serves as a general rigid substrate until the encapsulation process is completed, and implantable conductive lands adhering to the tape film.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the CVD amorphous silicon layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

Abstract: A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sets sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed from a silicon starved spacer materials, examples of which include SiOX, wherein X>2, SiNX, wherein X>1, or SiOXNY, wherein X+Y>2. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The first set of sidewall spacers act as a silicon diffusion barrier for preventing silicon from migrating from the gate electrode to the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.

Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

Abstract: A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).

Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

Abstract: A method of implanting dopants into a semiconductor structure is described wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. Also semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions are described.

Abstract: A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer comprises a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer.