Abstract: Certain implementations of the disclosed technology may include systems and methods for multibit code communications that can provide more than one bit per input port. In an example implementation, a method is provided that can include measuring an input voltage at an input port in communication with a device. The method can include comparing the measured input voltage with a plurality of predetermined reference voltage levels, and determining, based on the comparing, a device ID. The method can further include outputting the device ID. Certain implementations may further include compensating a signal associated with the device based on the identified device ID.

Abstract: Aspects of the present disclosure involve a system architecture for a policy driven disk IO throughput control for a hyper-converged storage provider. The computing architecture provides a flexible and real-time feature to the IO throughput management of a hyper-converged or converged infrastructure. In particular, through the use of centrally applied policy driven controls, the disk IO throughput allocation of different applications/clients of the converged infrastructure is gauged or otherwise controlled over the network bandwidth that link to the storage pool of the infrastructure. Through the use of the system architecture, the converged infrastructure may not utilize hard-coded disk resource allocation for each application/client in an isolated fashion, thereby allowing the IO throughput management to be flexible and agile in response to executed applications. Further, the IP throughput controlling and storage IP capacity of the converged infrastructure may be maintained separately.

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Abstract: A first communication unit 21 of a host-side transceiver device 20 performs communication based on an I2C communication scheme with a host device 10 and receives an access request signal sent from the host device 10. A second communication unit 22 performs communication based on a communication scheme different from the I2C communication scheme with a remote-side transceiver device 30 and sends the access request signal received by the first communication unit 21 to the remote-side transceiver device 30. The first communication unit 21 notifies the host device 10 that the first communication unit 21 has received the access request signal sent from the host device 10 before the access to the remote device 40 based on the access request signal sent from the second communication unit 22 ends.

Abstract: Debug trace statements from a firmware are captured during a boot cycle of a computer executing the firmware. The debug trace statements are written to a motherboard's Serial Peripheral Interface (“SPI”) device. A microcontroller's SPI device receives the debug trace statements from the motherboard's SPI device, transforms the data format of the debug trace statements, and transmits the transformed debug trace statements over a serial communications port of the microcontroller.

Abstract: A USB hub includes an upstream port; a first USB device control unit for performing packet format conversion; an FIFO circuit for storing data outputted from the first host; a second USB device control unit for performing packet format conversion; and a plurality of downstream ports. When any one of the downstream ports is coupled to the mobile device, if the first host commands the mobile device to switch to a host role from a device role, the mobile device temporarily disconnects from the USB hub, and the first host commands the USB hub to change an internal routing path. After the mobile device switches to the host role, the first host still performs the host role, and the first USB device control unit performs the device role; the mobile device performs the host role, and the second USB device control unit performs the device role.

Abstract: Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.

Abstract: According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips. In a first mode, the control chip enables the input buffer so as to activate the first transmission path and, in a second mode, disables the input buffer so as to activate the second transmission path.

Abstract: A mobile information communication apparatus includes a data processing device for sending plotting command/data to a display control device that controls the pixels of a display panel belonging to the mobile information communication apparatus. An interface device is provided which receives the plotting command/data generated by the data processing device and sends, based on plotting command/data, an external display signal to the external display device. The data processing device and the interface device are configured to send, from the interface device, a higher-resolution external display signal.

Abstract: A method of generating interaction activity information, performed by a device, is provided. The method includes establishing communication with at least one external apparatus; receiving first information about a user selectable function of the external apparatus; and generating second information, based on the first information, about a user selectable function of the device, wherein the user selectable function of the device corresponds to the user selectable function of the external device and can be performed in collaboration with the external device.

Abstract: A peripheral device capable of being worn, carried by a user, or used in an in-vehicle computer system operates in conjunction with an application to acquire, store, and present data relevant to a user's health, physical activity, environment, air quality, or other parameters of interest. For power efficient operation and enhanced performance, control parameters of the peripheral device such as duty cycle, sampling rate, and sleep state may be wirelessly and automatically controlled by the mobile device. Furthermore, the mobile application can provide a wireless energy signal to the peripheral device to recharge the battery of the peripheral device. The control parameters may be automatically controlled by the mobile application dependent on the user's location, activity, mode of transportation or other parameters without intervention from a user.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: An apparatus includes a circuit that includes a communication circuit to communicate information via a link using two communication modes. In the first communication mode, the communication circuit communicates information using a communication protocol. In the second communication mode, the communication circuit communicates information without triggering communication using the communication protocol.

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric are disclosed. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge allows writes to pass reads for a given source, but prevents reads from passing writes. The bridge forwards a write transaction out of the bridge when the write transaction is available for forwarding. The bridge forwards a read transaction from a given source out of the bridge when there are no outstanding write transactions for the given source that are older than the read transaction. The bridge prevents forwarding the read transaction from the given source out of the bridge when there are outstanding write transactions that are older than the read transaction for the given source.

Abstract: A storage system includes a holder, and a plurality of storage devices arranged along a line in the holder, each of the storage devices including first and second connection interfaces. Each of the first connection interfaces is electrically connected to a second connection interface of another storage device and each of the second connection interfaces is electrically connected to a first connection interface of another storage device, such that an electrical loop connection is formed through the plurality of the storage devices.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device emulates a first serial port at the embedded-system device. The embedded-system device exposes the first serial port to a host of the embedded-system device through a USB connection. The embedded-system device receives first command or data from the host through the first serial port. The embedded-system device processes the first command or data.

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Abstract: Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.

Abstract: A master device transmits a transaction to a target device. The transaction includes a transaction identifier. An ordering message is sent to the target device over a bus that is different than a communication channel that the transaction is transmitted over. The ordering message includes the transaction identifier. The target device adjusts an order of execution of the transaction by the target device based at least in part on receiving the ordering message.