Abstract: A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.

Abstract: An industrial automation system employing a mesh topology of input/output allows flexibility in pairing field devices and controllers though the I/O mesh. Field devices can be connected to the geographically closest I/O module channel without regard to the location of the necessary controller. Modular prefabrication and deployment of the I/O modules becomes less complex and less time consuming thereby reducing costs.

Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, each node containing at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being private to at least one node from among the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one of the first cache lines includes a first associated pointer pointing to a location of one of the second cache lines, and wherein at least one of the second cache lines includes a second associated pointer pointing to a location of one of the first cache lines.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.

Abstract: The present disclosure, in various aspects, describes technologies and techniques for use by a data storage device that includes a controller of a non-volatile memory (NVM). In one example, the controller applies a default storage format to a storage region of the NVM, the default storage format configuring the storage region as a number of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. The controller modifies the default storage format using a combination of horizontal dimension scaling and vertical dimension scaling based on a performance capability of the storage region to obtain a modified storage format. The controller applies the modified storage format to the storage region.

Abstract: A memory system includes a memory device and a controller. The memory device includes first and second memory groups. The controller includes a resource controller and first and second flash translation layer (FTL) cores. Each of the first and second FTL cores manages a plurality of logical addresses (LAs) that are mapped, respectively, to a plurality of physical addresses (PAs) of a corresponding memory group. The resource controller determines LA use rates of the first and second FTL cores, selects a source FTL core and a target FTL core from the first and second FTL cores using the LA use rates, and balances the LA use rates of the source FTL core and the target FTL core by moving data stored in storage spaces associated with a portion of the LAs from the source FTL core to storage spaces associated with the target FTL core.

Abstract: A write control method, an associated data storage device and the controller thereof are provided. The write control method includes: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a quantity of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.

Abstract: Embodiments of the present disclosure relate to method and device for data read/write. The method comprises: in response to receiving a first read/write request for a first target area, determining whether there is a second read/write request under execution in conflict with the first read/write request, a second target area for the second read/write request at least partially overlapping with the first target area, and at least one of the first read/write request and the second read/write request being a write request; and in response to determining there being the second read/write request in conflict, suspending the first read/write request while maintaining a sub-area of the first target area in an unlocked state, the sub-area not overlapping with the second target area.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes: a host for receiving and storing a host map segment; a memory device including a system block for storing map data, the memory device performing overall operations in response to an internal command; and a controller for generating the internal command for controlling the memory device in response to a host command received from the host. The controller receives the map data from the memory device and then stores the received map data, and generates the host map segment, using the map data, and then transmits the generated host map segment. A number of generatable host map segments is adjusted based on a work load calculated in a setting period.

Abstract: A method includes obtaining historical storage resource utilization data for a given set of storage resources of one or more storage systems, and generating a plurality of model-specific storage resource capacity predictions utilizing the historical storage resource utilization data and respective ones of a plurality of time series capacity prediction forecasting models. The method also includes selecting a subset of the model-specific storage resource capacity predictions having one or more designated characteristics, determining an overall storage resource capacity prediction based at least in part on a combination of the selected subset of the model-specific storage resource capacity predictions, and modifying a provisioning of storage resources of the one or more storage systems based at least in part on the overall storage resource capacity prediction.

Abstract: A peripheral device communicates with a central control device. The peripheral device includes a control circuit. The control circuit is configured to acquire, from another peripheral device, first information including a topic provided for the central control device or a user of the central control device, integrate the first information with second information which is included in the peripheral device and includes a topic provided for the central control device or the user of the central control device, to generate third information, and transmit the third information.

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.

Abstract: An embodiment of the present invention discloses a memory device. The memory device includes a memory controller, a calculation memory and a functional circuit. The calculation memory is coupled to the memory controller, and is configured to receive a plurality of first signals to output a plurality of second signals. Each of the second signals has a reference value. The functional circuit is coupled to the calculation memory, and is configured to indicate the second signal which has the greatest or the smallest reference value among the second signals.

Abstract: A gateway apparatus is provided, including: a storage unit storing a plurality of different filter information pieces each including an application target ECU configuration, a filter condition indicating a condition of data allowed to be transferred to the ECU and a filter version, in a manner associated with each other; a selection unit selecting, from among the plurality of different filter information pieces, a filter information piece whose application target ECU configuration corresponds to an ECU configuration of an ECU installed in the vehicle; a notification unit notifying an information processor of a filter version included in the filter information piece selected by the selection unit; and a filter processing unit judging whether or not data received from the information processor is to be transferred to the ECU installed in the vehicle in accordance with a filter condition included in the filter information piece selected by the selection unit.

Abstract: Apparatuses, systems, and methods are presented for column replacement. An input register, which includes a set of input divisions, may receive write data for a memory array. An output register, which includes a set of normal output divisions and a set of replacement output divisions, may output write data to an array. A column replacement circuit may selectively couple input divisions to output divisions. A column replacement circuit may couple normal output divisions for functional columns of an array to corresponding input divisions. A column replacement circuit may couple replacement output divisions for functional columns of an array to input divisions selected by the column replacement circuit, which may be corresponding input divisions or other input divisions.

Abstract: Predicting large data flushes by collecting usage data for system assets, analyzing the data using machine learning on each asset and the whole system to determine usage trends, predicting a next large data flush using a time-series model, and determining if a size of the predicted next flush size is too large relative to journal storage space in order to advance fast forward mode. Further, protecting history information by pausing distribution of data from journal volumes to replica volumes, taking storage-level snapshots of the replica and the journal volumes, storing a snapshot timestamp for each of the storage-level snapshots in a snapshot database prior to advancing the fast forward mode or un-pausing distribution.

Abstract: A data management method for a computer system including at least one processor and at least a first cache, a second cache, a victim buffer (VB), and a memory allocated to the at least one processor, includes selecting a victim cache line to be evicted from the first cache; finding a VB location corresponding to the victim cache line from a set of the VB; copying data of the victim cache line to a data field of the VB location; copying a backward pointer (BP) associated with the victim cache line to a BP field of the VB location; and reclaiming victim space of the first cache using the VB.

Abstract: An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. The string to be compressed extracted from the data register is stored to the look-ahead buffer. A string to be compressed includes Q characters, and a repeat flag is stored in the look-ahead buffer for each character in the string to be compressed. P instances are issued in parallel in each issue cycle. When all the characters included in P substrings corresponding to the P instances are identical to each other, the control circuit sets the repeat flags of the start characters corresponding to the last (P?1) instances among the P instances to a set state.

Abstract: A communication network includes a low integrity device, a high integrity device, a communication bus communicably coupling the low integrity device and the high integrity device together, and a communication guard inserted in-line along the communication bus. The communication guard includes a filter configured to store one or more rules defining at least one of a rate, a size, or a content type that is permissible for data transmissions from the low integrity device to the high integrity device; receive a respective data transmission from the low integrity device; evaluate characteristics of the respective data transmission relative to the one or more rules; and prevent the respective data transmission from passing through the communication guard to the high integrity device in response to the characteristics of the respective data transmission failing to comply with at least one of the one or more rules.