Abstract: A method for generating a security feature of a flash memory includes determining a memory block from a plurality of memory blocks in the flash memory; erasing data of the determined memory block of the flash memory; providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; and establishing a security feature based on the plurality of corresponding threshold voltages.

Abstract: Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.

Abstract: A data transmission method for transmitting first data to a plurality of physical remote target devices by a host system is provided. The method includes: generating a transmission instruction to transmit the first data to a network interface controller of the host system; transforming the first data into a plurality of second data and respectively recording the plurality of second data in a plurality of memory addresses of a memory of the network interface controller; and instructing the plurality of physical remote target devices to acquire the plurality of second data respectively from the plurality of memory addresses of the memory. In addition, a host system using the data transmission method is also provided.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to synchronize data bus access. An example system includes a first computing device to transmit a first synchronization pulse to second computing devices using a first bus, the first synchronization pulse to synchronize first timers of the second computing devices to trigger a data schedule including one or more data cycles, and transmit a second synchronization pulse to the second computing devices using the first bus, the second synchronization pulse to synchronize ones of the first timers and slot counters of the second computing devices to trigger the one or more data cycles. The example system further includes the second computing devices to transmit data to the first computing device using a second bus during the one or more data cycles, where each of the one or more data cycles is assigned to a corresponding one of the second computing devices.

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Abstract: A peripheral device controlling device according to an embodiment of the inventive concept includes a command queue for storing at least one Device to Device (D2D) command for data communication between a first peripheral device and a second peripheral device, a command parser for obtaining information related to the data communication from the at least one D2D command, and an orchestrator for controlling at least one of the first peripheral device and the second peripheral device to transfer data from the first peripheral device to the second peripheral device based on the acquired information.

Abstract: A system, method, and adaptor that facilitate data transmission are described. One example of the disclosed system facilitates the chip-to-chip transport of header descriptors and payloads. The system may include a source chip, a destination chip, and a set of queues describing buffer memory locations for staging header descriptors and payloads to be transferred from the source chip to the destination chip, where the set of queues are directly accessible to the source chip and to the destination chip.

Abstract: A semiconductor storage device includes a controller including a data direct memory access (DDMA) controller. The controller receives a plurality of read commands segmented into data transfer descriptors associated with data tags from a host device and directs a plurality of the data transfer descriptors to the DDMA controller. The DDMA controller pre-fetches one or more descriptors from the host device associated with one or more of the plurality of data tags, a first data tag having an associated number of descriptors corresponding to contiguous blocks of memory. The DDMA controller determines if the associated number of descriptors satisfies a threshold, and, if it does not, moves the first data tag to a first list, when at a head of the first list moves the first data tag to a second list, and when at a head of the second list, transmits the data associated with the first data tag.

Abstract: Examples include connecting an external physical layer device to a media access control device by determining a mode of a communications link between the external physical layer device and the media access control device; and when the mode of the communications link is serial gigabit media independent interface (SGMII), enabling an inter-integrated circuit (I2) interface between the external physical layer device and the media access control device, and setting a destination for management data input/output (MDIO) transactions to the external physical layer device.

Abstract: A method and system for maximizing bandwidth of a Peripheral Component Interconnect Express (PCIe) Peer-to-Peer (P2P) connection determine a maximum bandwidth and a maximum read request size of a first device, determining a maximum bandwidth and a minimum payload size of a second device, calculate a calculated maximum payload size of the second device by using the maximum read request size of the first device and a bandwidth ratio between the first device and the second device, compare the minimum payload size of the second device with the calculated maximum payload size, and set an operational payload size of the second device to the calculated maximum payload size when the calculated maximum payload size is equal to or greater than the minimum payload size.

Abstract: The present disclosure relates to an integrator for a storage device, a corresponding storage device and a method of manufacturing the same. The integrator comprises a base board comprising a first interface and a second interface; a connector coupled to the first interface of the base board, the connector being connectable with at least one server in the storage device; an input/output (I/O) part coupled to the second interface of the base board and connectable with an I/O device; and a switcher arranged on the base board and adapted to exchange data between the first interface and the second interface to support data transmission of the I/O device or other servers with the server via the integrator.

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Abstract: A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.

Abstract: A storage system includes a holder, and a plurality of storage devices arranged along a line in the holder, each of the storage devices including first and second connection interfaces. Each of the first connection interfaces is electrically connected to a second connection interface of another storage device and each of the second connection interfaces is electrically connected to a first connection interface of another storage device, such that an electrical loop connection is formed through the plurality of the storage devices.

Abstract: A power-up control circuit is provided and includes a pull-down resistor, a pull-down switch, and an enable device. A first terminal of the pull-down resistor is electrically connected to a configuration channel pin of a USB Type-C connection port. The pull-down switch is electrically connected to a second terminal of the pull-down resistor and a ground node. The enable device is electrically connected to the pull-down switch and the configuration channel pin. When receiving a voltage detection signal which is transmitted by a dual-role port device through the configuration channel pin, the enable device turns on the pull-down switch to electrically connect the pull-down resistor to the ground node, so that the dual-role port device detects the pull-down resistor through the configuration channel pin and supplies power to the microcontroller through a power supply pin to keep the microcontroller in the power-up status.

Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.

Abstract: An apparatus and a computer program product includes non-transitory computer readable storage media embodying program instructions. The program instructions are executable by a baseboard management controller (BMC) to receive a request to install a hardware component in a compute node, identify a current hardware configuration of the compute node, and identify a plurality of available locations within the compute node for installation of the requested component. Still further, the BMC may identify, for each available location, a historical performance database record that includes a performance score for a component installed in the same location as the available location, has the same component type as the requested component, and was collected from a compute node having the same hardware configuration as the current compute node. The BMC may select an available location that has the greatest performance score for the component, and generate output indicating the selected location for installation.