Patents Examined by Christopher Birkhimer
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Patent number: 9268649Abstract: A disk drive is disclosed comprising a disk comprising a plurality of refresh regions, each refresh region comprising a range of logical block addresses (LBAs). The disk drive further comprises a recent write streams list comprising one or more entries, each entry representing an LBA stream. The disk drive further comprises a head actuated radially over the disk to write data to and read data from the disk, and control circuitry coupled to the head, wherein the control circuitry is operable to execute a write command comprising one or more LBAs, determine whether the one or more LBAs are sequential to an entry in the recent write streams list, modify an entry in the recent write streams list when the one or more LBAs are sequential to the entry, and utilize the modified entry to determine whether to reset a refresh counter associated with a refresh region.Type: GrantFiled: June 23, 2011Date of Patent: February 23, 2016Assignee: Western Digital Technologies, Inc.Inventors: Robert Morelli Fallone, Edwin Scott Olds
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Patent number: 9075719Abstract: A storage system is migrated without stopping service provision by a host computer. By this means, in a migration-source storage system, data of the cache memory is destaged, and, next, data received from the host computer is directly written in a logical unit by bypassing the cache memory. On the other hand, in a migration-destination storage system, communication with the migration-source storage system is performed to set setting information of a logical unit of the migration object into a logical unit management table and set a writing mode for the cache memory to a cache-bypass mode. After that, the migration-source storage system blocks a path to the host computer. The migration-destination storage system receives a report of the path block from the migration-source storage system and then opens a path between the own system and the host computer.Type: GrantFiled: February 10, 2012Date of Patent: July 7, 2015Assignee: Hitachi, Ltd.Inventors: Mika Teranishi, Hiroji Shibuya, Shunji Murayama, Toshio Kimura, Kazushige Nagamatsu
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Patent number: 9075723Abstract: A plurality of tracks is examined for meeting criteria for a discard scan. In lieu of waiting for a completion of a track access operation, at least one of the plurality of tracks is marked for demotion. An additional discard scan may be subsequently performed for tracks not previously demoted. The discard and additional discard scans may proceed in two phases.Type: GrantFiled: June 17, 2011Date of Patent: July 7, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Carol S. Mellgren, Kenneth W. Todd
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Patent number: 9058117Abstract: Described in detail herein are systems and methods for single instancing blocks of data in a data storage system. For example, the data storage system may include multiple computing devices (e.g., client computing devices) that store primary data. The data storage system may also include a secondary storage computing device, a single instance database, and one or more storage devices that store copies of the primary data (e.g., secondary copies, tertiary copies, etc.). The secondary storage computing device receives blocks of data from the computing devices and accesses the single instance database to determine whether the blocks of data are unique (meaning that no instances of the blocks of data are stored on the storage devices). If a block of data is unique, the single instance database stores it on a storage device. If not, the secondary storage computing device can avoid storing the block of data on the storage devices.Type: GrantFiled: October 9, 2013Date of Patent: June 16, 2015Assignee: CommVault Systems, Inc.Inventors: Deepak Raghunath Attarde, Rajiv Kottomtharayil, Manoj Kumar Vijayan
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Patent number: 9058212Abstract: In a device having a memory accessed as multiple pages, two or more pages of the multiple pages having identical content are identified. While the two or more pages are being identified, other processes running in the device are allowed to use the two or more pages, including being allowed to change cache attributes of each of the two or more pages. The two or more pages are combined into a single combined page (e.g., a newly allocated page of the multiple pages), and a process page record having multiple entries pointing to the multiple pages is updated so that entries that previously pointed to one of the two or more pages instead point to the single page.Type: GrantFiled: March 21, 2011Date of Patent: June 16, 2015Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Landy Wang, Mehmet Iyigun, Yevgeniy Bak, Vijay Sundaram, Pavlo L. Lebedynskiy
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Patent number: 8949565Abstract: A system reserves and manages a hidden service partition through components of the hardware platform of a computing device. The hidden partition is not accessible by way of a host operating system on the computing device. A hardware platform controller provisions a portion of nonvolatile storage through configuration settings of the hardware platform controller. When the host system requests settings related to storage in the system, the request is routed through the interfaces of the hardware platform, and the hardware platform controller reports in accordance with the configuration settings, hiding the service partition. The hidden partition is dynamically modifiable through secure remote access to the hardware platform controller, not through the host system such as operating system or BIOS.Type: GrantFiled: December 27, 2009Date of Patent: February 3, 2015Assignee: Intel CorporationInventors: Hormuzd M. Khosravi, Yasser Rasheed, Venkat R. Gokulrangan
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Patent number: 8949555Abstract: In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.Type: GrantFiled: June 16, 2011Date of Patent: February 3, 2015Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Shibabrata Mondal, Ajith Kumar
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Patent number: 8943276Abstract: A plurality of tracks is examined for meeting criteria for a discard scan. In lieu of waiting for a completion of a track access operation, at least one of the plurality of tracks is marked for demotion. An additional discard scan may be subsequently performed for tracks not previously demoted. The discard and additional discard scans may proceed in two phases.Type: GrantFiled: March 14, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Lokesh M. Gupta, Carol S. Mellgren, Kenneth W. Todd
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Patent number: 8918610Abstract: A chip including a processor for performing a predetermined operation, a provider for providing a clock signal, with which the processor is clocked, a counter for decrementing or incrementing a count based on the clock signal, a monitor for signaling the predetermined operation to be prevented, depending on the count, and a non-volatile storage for non-volatily storing the count.Type: GrantFiled: December 8, 2004Date of Patent: December 23, 2014Assignee: Infineon Technologies AGInventor: Peter Laackmann
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Patent number: 8914591Abstract: An information processing apparatus processes data to be processed while accessing data to be processed that is stored in a memory or a HDD. The information processing apparatus determines the process content and calculates the access number to the HDD based on the determined process content and the content of data to be processed. The information processing apparatus also decides to store data to be processed in the memory when the access number is more than or equal to a threshold value. The information processing apparatus decides to store data to be processed in the HDD when the access number is less than the threshold value.Type: GrantFiled: February 17, 2012Date of Patent: December 16, 2014Assignee: Canon Kabushiki KaishaInventor: Hiromasa Kawasaki
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Patent number: 8914606Abstract: According to at least one embodiment, a method comprises partitioning a computer system into a plurality of soft partitions that each run an operating system. The method further comprises instantiating a separate firmware instance for each of the plurality of soft partitions, wherein each of the firmware instances provides a pre-defined firmware interface for the operating system of its respective soft partition.Type: GrantFiled: January 20, 2005Date of Patent: December 16, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventor: Bradley G. Culter
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Patent number: 8909881Abstract: A system and method of creating archive copies of data sets is described. In some examples, the system creates an archive copy from an original data set. In some examples, the system creates an archive copy when creating a recovery copy for a data set. In some examples, the system creates a copy without redundant data, and then encrypts the data set.Type: GrantFiled: March 5, 2013Date of Patent: December 9, 2014Assignee: CommVault Systems, Inc.Inventors: Alan Bunte, Anand Prahlad, Brian Brockway
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Patent number: 8904106Abstract: In a method for allocating space on a logical disk, a computer receives an allocation request to allocate a number of requested logical disk extents. The computer selects one of a first group having an array of logical disk extents and a second group having an array of logical disk extents. The computer selects a group having a number of free logical disk extents that is greater than or equal to the number of requested logical disk extents. The logical disk extents in the array of the first group and in the array of the second group correspond to disk blocks on a logical disk. The logical disk spans one or more physical random access disks. The computer locks the selected group to prevent allocating a logical disk extent other than in response to the allocation request.Type: GrantFiled: June 22, 2011Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Adekunle Bello, Aruna Yedavilli
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Patent number: 8898394Abstract: A storage apparatus for controlling a storage unit includes a cache memory for temporarily storing data to be stored in the storage unit, and a processor for executing a process including receiving unit data which is divided from data to be migrated, calculating first checksum data from the received unit data, storing the unit data and the first checksum data to the cache memory, reading out the stored unit data and the first checksum data from the cache memory, calculating second checksum data from the read out unit data, storing the unit data to the storage unit, and determining whether data migration has been performed properly by comparing the first checksum data to the second checksum data.Type: GrantFiled: August 6, 2010Date of Patent: November 25, 2014Assignee: Fujitsu LimitedInventors: Norio Kondo, Satoshi Konno, Ken-ichiroh Tango
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Patent number: 8898410Abstract: A method includes determining which of a plurality of blocks of data in a data storage device having a plurality of memory devices to copy during garbage collection using a cost function based on a number of free pages and a number of replicated pages in each of the blocks, where the replicated pages include replicated data that is a copy of data stored in another storage device and determining not to copy one or more of the blocks of data during garbage collection based on the cost function.Type: GrantFiled: February 20, 2013Date of Patent: November 25, 2014Assignee: Google Inc.Inventor: Daniel Ari Ehrenberg
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Patent number: 8874838Abstract: A network device allocates a particular number of memory blocks in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and creates a list of additional memory blocks in an external TCAM of the network device. The network device also receives, by the external TCAM, a request for an additional memory block to provide one or more rules from one of the multiple databases, and allocates, by the external TCAM and to the requesting database, an additional memory block from the list of additional memory blocks.Type: GrantFiled: December 28, 2009Date of Patent: October 28, 2014Assignee: Juniper Networks, Inc.Inventors: Sandip Shah, Jing Ai
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Patent number: 8874855Abstract: Techniques are generally described for methods, systems, data processing devices and computer readable media related to multi-core parallel processing directory-based cache coherence. Example systems may include one multi-core processor or multiple multi-core processors. An example multi-core processor includes a plurality of processor cores, each of the processor cores having a respective cache. The system may further include a main memory coupled to each multi-core processor. A directory descriptor cache may be associated with the plurality of the processor cores, where the directory descriptor cache may be configured to store a plurality of directory descriptors. Each of the directory descriptors may provide an indication of the cache sharing status of a respective cache-line-sized row of the main memory.Type: GrantFiled: December 28, 2009Date of Patent: October 28, 2014Assignee: Empire Technology Development LLCInventor: Tom Conte
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Patent number: 8874839Abstract: An electronic system, and a method and an apparatus for saving data of the electronic system are provided. The electrical system includes a central processing unit (CPU), a temperature sensor, a first controller, a second controller, a first storage device and a second storage device. When the CPU enters a suspend mode and the first controller detects a temperature of the electronic system to be lower than a threshold value through the temperature sensor, the second controller notify the application program to trigger the CPU to enter a hibernation mode, and operation data is moved from the first storage device to the second storage device.Type: GrantFiled: February 15, 2012Date of Patent: October 28, 2014Assignee: Getac Technology CorporationInventor: Chia-Chang Chiu
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Patent number: 8874856Abstract: A false sharing detecting apparatus for analyzing a multi-thread application, the false sharing detecting apparatus includes an operation set detecting unit configured to detect an operation set having a chance of causing performance degradation due to false sharing, and a probability calculation unit configured to calculate a first probability defined as a probability that the detected operation set is to be executed according to an execution pattern causing performance degradation due to false sharing, and calculate a second probability based on the calculated first probability. The second probability is defined as a probability that performance degradation due to false sharing occurs with respect to an operation included in the detected operation set.Type: GrantFiled: June 17, 2011Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Hyun Cho, Sung-Do Moon
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Patent number: 8868852Abstract: A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.Type: GrantFiled: June 22, 2011Date of Patent: October 21, 2014Assignee: Marvell World Trade Ltd.Inventors: Chi Kong Lee, Siu-Hung Fred Au, Jungil Park, Hyunsuk Shin