Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.

Abstract: A management apparatus, a management method, and a storage management system that more specifically manage power consumption, making it easy to analyze problems relating to power consumption or properly relocate data are provided. A power consumption for each of a plurality of memory apparatus groups each consisting of a plurality of memory apparatuses in a storage system is computed based on a performance for each of a plurality of logical storage extents defined in a plurality of storage extents provided by each of the memory apparatus groups, and a value of the power consumption for each of one or more of the memory apparatus groups obtained by the computation is output together with information on an access status of each of the corresponding logical storage extents.

Abstract: Typical computer programs may incur costly memory errors that result in corrupted data. A new memory model is presented wherein it may be determined that certain data is critical and critical data may be stored and protected during computer application execution. Critical Memory allows that data determined to be critical may be stored and retrieved using functions enabled to increase the reliability of the data. Critical Memory presents a memory model where a subset of memory designated as critical memory may be used to store a subset of data deemed critical data. Probabilistic guarantees of data value consistency are provided by the employment of the new memory model. The memory model and functions presented are compatible with existing third-party libraries such that third-party libraries may be compatibly called from processes using critical memory.

Abstract: A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

Abstract: Backing up data from a client includes providing a direct coupling between the client and a portable storage device, copying full backup data from the client to the portable storage device using the direct coupling, and performing at least one incremental backup from the client to the backup site through a network that is separate from the direct coupling. The at least one incremental backup is based on the prior full backup. The network may be the Internet. Following copying full backup data to the portable storage device, the portable storage device may be shipped from the client to the backup site. The direct coupling may be USB, Firewire, or eSATA. Only a subset of data corresponding to a backup dataset may be copied from the client to the portable storage device.

Abstract: A transactional memory system, method and apparatus are disclosed. An embodiment of the method includes attempting to acquire a write lock provided by an implementation of a software transactional memory (STM) system for each of a set of memory locations of the STM; if a write lock is acquired for each of the set of memory locations, comparing the value in each of the set of memory locations to a corresponding expected value; and if the comparing yields the same, predetermined result for each of the set of memory locations, storing in each memory location a corresponding new value. Other embodiments are also described and claimed.

Abstract: By exploiting an early release facility that may be provided by certain transactional memory designs, we facilitate transaction software constructs that operate on dynamically-sized data structures and/or other data structures for which traversal may be data dependent. Absent exploitation of such a facility, the act of traversing the data structure would typically introduce corresponding locations into the read set of a transaction, and a subsequent modification of any of the previously traversed locations would result in abortion of the traversing transaction. By exploiting an early release facility such as described herein, a transaction may release the locations that it has previously read in traversal and thereby eliminate such read locations as a source of conflict with other concurrently executing computations or transactions. In this way, concurrency may be enhanced while still employing a conceptually simple and convenient coordination facility.

Abstract: When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.

Abstract: For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.