Abstract: In the storage system, a storage apparatus includes a disk device for storing write data from a host computer as a primary volume and copied data of write data as a secondary volume, and a disk controller for collecting and managing status information of a plurality of copy pairs from the disk device with a primary volume and a secondary volume as a single copy pair. The disk controller monitors the status information of the plurality of copy pairs according to the status of failure, and, upon receiving a status notification command, transfers the detailed information concerning a copy pair as the status information of the copy pair subject to a failure, and flag information showing the overall status of all other copy pairs as status information of such other copy pairs.

Abstract: Upon the arrival at a memory device of one or more data chunks associated with respective logical addresses, each data chunk is assigned a signature, stored in a first location, and copied to a second location. The copy is assigned a signature that matches the signature of its parent data chunk. Before erasing a memory block that includes one or more data chunks, it first is verified that those data chunks have been copied, i.e., that copies of all the data chunks in the block, with matching signatures, exist in the memory device.

Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic, a reorder table and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The reorder table includes two or more table elements. Each table element includes a shared address component and an independent address component corresponding to each of the two or more independently addressable subchannels. The transaction assembler combines the shared and independent address components in a reorder table element and issue a single memory transaction.

Abstract: In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.

Abstract: A data processor includes a flash memory that stores a plurality of types of data therein, a random access memory that stores record data information therein, and a controller that can access the flash memory and the RAM. The record data information indicates a head address in the flash memory and a data length corresponding to latest data of each of the plurality of types of data. The controller reads, from the flash memory, the latest data of a type of a reading target among the plurality of types of data, with reference to the record data information.

Abstract: A method and corresponding apparatus for enhancing the capacity of communication and memory devices, said method comprising the representation of information by lattice points confined to a cubic region of an n-dimensional space, by means of which for example capacity gains of 50% or 100% and more may be achieved, relative to ‘conventional’ communication and storage methods.

Abstract: A flash memory device includes a memory cell array, a peri circuit unit, an I/O controller, and a controller. The memory cell array includes a plurality of memory cells respectively connected to a plurality of bit line pairs and a plurality word lines. The peri circuit unit is configured to program data into the memory cell array or read data stored in the memory cell array in response to a command input through a control bus. The I/O controller is configured to receive data for programming and supply the data to the peri circuit unit in response to a command provided through a data input/output (I/O) bus. The controller is configured to control the I/O controller to perform a voltage setup operation for a program while the data for program is received.

Abstract: An apparatus and method for providing media content to electronic equipment includes transferring media content to the electronic equipment, and using rules to determine how pre-existing media content and the cached media content are stored in memory when free memory in the electronic equipment is insufficient to store the cached media content. At least part of the transferred media content is cached in memory of the electronic equipment for use at a later time.

Abstract: The present invention discloses a method for processing data of a flash memory by differentiating levels, which includes steps of separating the communication between a host and a flash memory by a high-level translation layer (HTL) and a low-level abstraction layer (LAL). The HTL receives commands and logical addresses from the host and translates the received logical addresses to the physical addresses of the flash memory. The LAL executes data processing to the corresponding memory cells according to the commands and the physical addresses from the HTL. Since the LAL is disposed between the HTL and the flash memory, the HTL is irrelevant to the structure of the flash memory, and does not have to re-designed with the flash memory which is replaced with another new flash memory.

Abstract: A control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following processing steps. In Step 1, a storage space of every channel is partitioned into a plurality of storage units of equal size. In Step 2, at least one logical strip is set by which the storage units with discrete physical addresses across a plurality of channels are organized into a continuous logical space. In Step 3, during data reading/writing operation, the data is divided according to a size of each local strip, the divided data is mapped to the storage units of every channel, and a parallel reading/writing operation is performed across the channels. This method may increase the efficiency of reading and writing operations of the storage device and prolong the operating life span of the device.

Abstract: A self-adaptive control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following steps. Storage space of every channel is divided into a plurality of storage units of equal size. At least one logical strip is set by which the storage units with discrete physical addresses across the channels are organized into a continuous logical space, and a logical strip variable is set for determining the storage units organized by the logical strip. Historical operation information of the storage device is obtained statistically, and the logical strip variable is dynamically adjusted according to the obtained operation information. During data interaction, the data is divided according to the logical strip variable, the divided data is mapped to the storage units of every channel, and parallel reading and writing operations are performed among the channels.

Abstract: A computer-implemented method for off-host backups of striped volumes may include identifying a striped volume of data on which to perform an off-host backup operation. The computer-implemented method may also include identifying a plurality of storage devices underlying the striped volume of data. The computer-implemented method may further include identifying stripe-aware extent metadata for the off-host backup operation. The computer-implemented method may additionally include reading data for the off-host backup operation from the plurality of storage devices in parallel using the stripe-aware extent metadata. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system and method optimizing data throughput to a processor from a storage device having sequential data access capabilities where the processor enables its data cache for memory operations involving the storage device. The system includes a processor coupled to the data storage device, e.g., a NAND flash memory. The processor establishes an address window used as a cache (CW) for reading data from the flash memory and also establishes a non-cacheable address window (NCW) for commands, address delivery and writes to the flash memory. The CW is sized to be larger than the processor data cache to ensure that reads from the flash memory always encounter a cache-miss so that read data is obtained directly from the flash memory. By reading through the CW from the flash memory, the processor takes advantage of bursting, pipelining and data prefetch efficiencies which significantly increase data throughput.

Abstract: An memory device including a data region storing a main data, a first index region storing a count data, and a second index region storing an inverted count data, where the data region, the first index region, and the second index region are included in one logical address.

Abstract: A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is used as a first-level cache for small amount of data, and an external RAM of the data packet processing chip is used as a second-level cache for large amount of data. In this way, some data packets are read and written within the chip and not all data packets have to be read and written through the external RAM. A data packet reading/writing operation may be performed to the external RAM by a BANK interleave mode.

Abstract: Parallel, coordinated, and optimized access of real Base and Alias DASDs by one or more virtual machines, each utilizing one or more virtual Base and Alias DASDs. Each of a plurality of virtual machines defines a virtual Base DASD device and a modified operating system may coordinate the virtual machine activity on real Base and Alias devices to maximize overall system throughput. In more complex embodiments, one or more virtual machines define one or more virtual Bases and associated virtual Alias devices in which case wherein the embodiments described coordinate their activity on one or more real Base and Alias devices to maximize overall system throughput.

Abstract: Provided are a method, system, and an article of manufacture, wherein resources corresponding to at least one copy pool are acquired, and wherein the at least one copy pool has been defined for a first primary storage pool of a storage hierarchy. The acquired resources are retained, in response to determining that data cannot be written to the first primary storage pool. The data is written to the at least one copy pool, in response to writing the data to a second primary storage pool of the storage hierarchy.

Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.

Abstract: The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service creates a storage map, and sending said storage map to an application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating a cache map. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating an indication of one or more storage locations that have been allocated to store information for the application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating the storage map in response to receiving a request for the storage map from the application.

Abstract: A system and method of creating archive copies of data sets is described. In some examples, the system creates an archive copy from an original data set. In some examples, the system creates an archive copy when creating a recovery copy for a data set. In some examples, the system creates a copy without redundant data, and then encrypts the data set.