Patents Examined by Christopher Birkhimer
  • Patent number: 8566549
    Abstract: Synchronization of data layouts and resource utilizations at one or more remote replica sites with the workload and data tiering decisions being made at the primary site allows for an efficient and effective workload support transfer in the event of site failover from a primary site to a remote site. Relevant data access information about workload being supported at the primary site is collected and from that raw information, characterized data access information is generated that condenses the raw data access information or otherwise provides relevant encapsulated information about the raw data access information. The characterized data access information is transmitted to the one or more remote sites allowing each remote site to make its own independent decisions on how best to utilize its available resources to match the performance requirements currently being supported by the primary site.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 22, 2013
    Assignee: EMC Corporation
    Inventors: Barry Burke, Alexandr Veprinsky, Amnon Naamad, John T. Fitzgerald
  • Patent number: 8527737
    Abstract: The described embodiments determine if two addressed memory regions overlap. First, a first address for a first memory region and a second address for a second memory region are received. Then a composite address is generated from the first and second addresses. Next, an upper subset and a lower subset of the bits in the addresses are determined. Then, using the upper and lower subsets of the addresses, a determination is made whether the addresses meet a condition from a set of conditions. If so, a determination is made whether the lower subset of the bits in the addresses meet a criteria from a set of criteria. Based on the determination whether the lower subset of the bits in the addresses meet a criteria, a determination is made whether the memory regions overlap or do not overlap.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: September 3, 2013
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Patent number: 8499115
    Abstract: A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded. The value of the most significant bits is output. The value of a neighboring bit of each storage unit is obtained and recorded. The neighboring bit neighbors the most significant bit. The value of the neighboring bits is output.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: July 30, 2013
    Assignee: Via Technologies, Inc.
    Inventor: Ming-Xing Gao
  • Patent number: 8489825
    Abstract: A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits from a register file (RF) into a memory (M) is described. The memory is arranged for storage of a vector of storage data elements in locations (M1, . . . , M5) having a size of m bits, wherein m>n. The method comprises the steps of: exchanging bits (S2) between process data elements in the vector stored in mutually subsequent register elements, the exchanging resulting in a vector of modified data elements (DmI, . . . , Dm8), shuffling (S3) groups of k subsequent bits in the resulting vector, —storing (S4) the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory (M).
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: July 16, 2013
    Assignee: ST-Ericsson SA
    Inventor: Cornelis H. Van Berkel
  • Patent number: 8484411
    Abstract: A method and system for accessing a dynamic random access memory (DRAM) is provided. A memory controller includes a content addressable memory (CAM) based decision control module for determining a next best access request for the DRAM. The CAM based decision control module includes a CAM access storage module for storing access requests, a next access table module for storing the next best access request, and a decision logic module for determining the next best access request based on results from the CAM access storage module and the next access table module. Further, the memory controller includes a DRAM access control interface for implementing signaling required to access the DRAM. The method includes storing access requests in a CAM access storage module. The method includes determining which of the stored access requests is a next best access request. Further, the method includes processing the next best access request.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 9, 2013
    Assignee: Synopsys Inc.
    Inventors: Raghavan Menon, Raj Mahajan
  • Patent number: 8464018
    Abstract: Provided are a method, system, and an article of manufacture, wherein resources corresponding to at least one copy pool are acquired, and wherein the at least one copy pool has been defined for a first primary storage pool of a storage hierarchy. The acquired resources are retained, in response to determining that data cannot be written to the first primary storage pool. The data is written to the at least one copy pool, in response to writing the data to a second primary storage pool of the storage hierarchy.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: Howard Newton Martin, Rosa Tesller Plaza
  • Patent number: 8452920
    Abstract: A method of controlling a dynamic random access memory (DRAM) and a DRAM memory controller is provided. An example DRAM memory controller includes a content addressable memory (CAM) based decision control module. The CAM based decision control module includes a CAM access storage module, a next access table module, and a decision logic module. Further, the DRAM memory controller includes a DRAM access control interface. The method includes detecting a request for a read-modify-write operation. The method also includes creating a read access request and a write access request based on the detecting. Further, the method includes prioritizing the read access request and the write access request. Moreover, the method includes executing the read access request and the write access request based on the prioritizing.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 28, 2013
    Assignee: Synopsys Inc.
    Inventors: Raghavan Menon, Raj Mahajan
  • Patent number: 8452939
    Abstract: The present invention provides a method for estimating a capacity usage status of a storage unit, where the storage unit includes a plurality of sectors. The method includes: estimating capacity usage statuses of a portion of sectors; and utilizing a controller to estimate the capacity usage status of the storage unit according to the estimated capacity usage statuses of the portion of sectors in a situation of not estimating capacity usage statuses of all of the sectors of the storage unit.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: May 28, 2013
    Assignee: JMicron Technology Corp.
    Inventors: Shu-Yi Lin, Kai-Lung Cheng, Yuan-Chu Yu
  • Patent number: 8447922
    Abstract: A memory controller, a nonvolatile storage device, an access device, and a nonvolatile storage system enable the storage architecture to be changed flexibly for intended use that can be changed variously. A nonvolatile storage system (100) sets a temporary area (23) and a normal access area of a nonvolatile memory (22) based on a use condition designated by a use condition designation unit (11) of an access device (1). This structure enables the nonvolatile storage system (100) to change the temporary area (23) and the normal access area (24) to be prepared in the nonvolatile memory (22) by changing the use condition in accordance with intended use. In other words, the nonvolatile storage system (100) enables the storage architecture to be changed flexibly for intended use that can be changed variously.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Takashi Ogasawara
  • Patent number: 8447944
    Abstract: An object is to enable efficient shredding of recording media in association with migration. An information processing device (a server device 3) receives a data input/output request in a unit of a file transmitted from a client device 2, and performs writing and reading of data to and from a storage system 10 having a recording medium (hard disk drive 171) in which a file entity specified in the received data input/output request is stored in units of data blocks. The information processing device is communicatively coupled to a different storage device which is a migration destination of data. In the case where after the migration of certain data, different data is written in a data block of the certain data in an overlapped manner, the data block is not shredded if the data block is already shredded related to either of the overlapped certain and the different data after the migration.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: May 21, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Nobuyuki Saika
  • Patent number: 8447926
    Abstract: A method of controlling an ODD archive system comprising three or more ODDs is provided comprising storing information on a parity drive in a memory, and setting a parity drive in which parity data is to be recorded based on the information when data recording is requested in a RAID 3 or 4 manner. The information on the parity drive may include a cumulative value of number of times by which each ODD has been set as the parity drive up to now. Or the information on the parity drive may be managed for each of one or more magazine having optical discs the number of which is equal to or less than the number of ODDs included in the archive system.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: May 21, 2013
    Assignee: Hitachi-LG Data Storage Korea, Inc.
    Inventor: Seungpill Kong
  • Patent number: 8433849
    Abstract: The invention concerns a distributed object storage system (1) that comprises a spreading module (410) which makes a selection of a number of storage elements (300) being larger or equal to a desired spreading width by means of a spreading policy that comprises rules for selecting storage elements (300) in function of a first hierarchy level identifier (70.1) and/or a second hierarchy level identifier (70.2).
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 30, 2013
    Assignee: Amplidata NV
    Inventors: Frederik De Schrijver, Romain Raymond Agnes Slootmaekers, Bastiaan Stougie, Kristof Mark Guy De Spiegeleer, Wim De Wispelaere, Wouter Van Eetvelde
  • Patent number: 8429346
    Abstract: Methods and systems are disclosed for relocating data in a physical storage pool comprising a plurality of storage tiers having differing performance characteristics, the physical storage pool being mapped into one or more logical units, each logical unit comprising a plurality of logical slices of data storage. The methods and systems can involve receiving a relocation list, the relocation list including, for each of a plurality of logical slices, a slice identifier, a temperature value, and a current physical location, determining a destination tier for each logical slice on the relocation list, evaluating for each logical slice on the relocation list a performance gain expected to be achieved by moving the logical slice from its current physical location to a new location in the destination tier, and relocating data in a logical slice from its current physical location to the new location based on the evaluation.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 23, 2013
    Assignee: EMC Corporation
    Inventors: Xiangping Chen, Khang Can, Manish Madhukar, David Harvey, Dean Throop, Mark Ku
  • Patent number: 8412907
    Abstract: A method of allocating resources in a data processing system is disclosed. The method includes an application designing a page reallocation scheme and sending said page reallocation scheme from said application to a kernel service that is responsible for allocation of storage locations.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 2, 2013
    Assignee: Google Inc.
    Inventors: Andrew Dunshea, Diane Garza Flemming
  • Patent number: 8407432
    Abstract: A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 26, 2013
    Assignee: Intel Corporation
    Inventors: Zhong-Ning Cai, Krishnakanth V. Sistla, Yen-Cheng Liu, Jeffrey D. Gilbert
  • Patent number: 8402216
    Abstract: A computer-implemented method for off-host backups may include identifying a striped volume of data on which to perform an off-host backup. The computer-implemented method may also include generating stripe-aware extent metadata for the off-host backup operation. The computer-implemented method may further include performing the off-host backup operation using the stripe-aware extent metadata. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: March 19, 2013
    Assignee: Symantec Corporation
    Inventors: Kuldeep Nagarkar, Ashish Govind Khurange
  • Patent number: 8402223
    Abstract: Embodiments are directed to efficiently determining which cache entries are to be evicted from memory and to incorporating a probability of reuse estimation in a cache entry eviction determination. A computer system with multiple different caches accesses a cache entry. The computer system determines an entry cost value for the accessed cache entry. The entry cost value indicates an amount of time the computer system is slowed down by to load the cache entry into cache memory. The computer system determines an opportunity cost value for the computing system caches. The opportunity cost value indicates an amount of time by which the computer system is slowed down while performing other operations that could have used the cache entry's cache memory space. Upon determining that the entry cost value is lower than the opportunity cost value, the computer system probabilistically evicts the cache entry from cache memory.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 19, 2013
    Assignee: Microsoft Corporation
    Inventors: Adrian Birka, Adam Prout, Sangeetha Shekar, Georgiy I. Reynya
  • Patent number: 8392677
    Abstract: A system and method of creating archive copies of data sets is described. In some examples, the system creates an archive copy from an original data set. In some examples, the system creates an archive copy when creating a recovery copy for a data set. In some examples, the system creates a copy without redundant data, and then encrypts the data set.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 5, 2013
    Assignee: CommVault Systems, Inc.
    Inventors: Alan Bunte, Anand Prahlad, Brian Brockway
  • Patent number: 8370567
    Abstract: A method for storing data, including receiving a request to write a first datum defined using a first object ID and a first offset ID to persistent storage. The method further including determining a first physical address in the persistent storage, where the first physical address comprises a first block ID and first sub block ID. The method further includes writing the first datum to the first physical address, generating a first table of contents entry (TE) comprising the first object ID, the first offset ID, and the first sub block ID, and writing the first TE to a second physical address in the persistent storage, where the second physical address comprises the first block ID and a second sub block ID corresponding to the second sub block ID, and where the second sub block is located within a first block corresponding to the first block ID.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 5, 2013
    Assignee: DSSD, Inc.
    Inventors: Jeffrey S. Bonwick, Michael W. Shapiro
  • Patent number: 8370578
    Abstract: Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided. A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: February 5, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Yoshii, Mitsuru Inoue, Kentaro Shimada, Sadahiro Sugimoto