Abstract: A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.

Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.

Abstract: A disk drive is disclosed comprising a head actuated over a rotatable disk. A write operation is processed to write data on the disk using the head, wherein prior to writing the data on the disk, logical-to-physical mapping information is stored in a circular buffer, wherein the logical-to-physical mapping information identifies locations on the disk to write the data. A plurality of metadata files are written on the disk using the head, wherein the plurality of metadata files are interspersed with the data on the disk and each of the metadata files includes contents of the circular buffer at a time the metadata file is written on the disk. When the write operation is aborted, the logical-to-physical mapping information in the circular buffer is modified to identify the locations on the disk actually written.

Abstract: Provided are a computer program product, system, and method for interfacing with point-in-time copy service architecture to create a point-in-time copy of a volume in a storage used by an application. A point-in-time copy request is processed to perform a point-in-time copy with respect to the volume in the storage, wherein the request indicates at least one exit, wherein the exit indicates when the exit is to be invoked with respect to an operation of the point-in-time copy and indicates a location of an executable object to execute when the exit is invoked. Communicating with the point-in-time copy service to prepare for the point-in-time copy. For each exit, determining from the exit when to invoke the exit and executing the executable object for the exit to invoke to perform operations related to the point-in-time copy. The point-in-time copy service is called to perform the point-in-time copy operation of the volume.

Abstract: In an information recording medium in which storage capacity per recording layer has increased so much that the size of an SBM varies with those of spare areas, there is mutual dependence between a DDS and an SBM and it is difficult to retrieve disc management information as intended. In an information recording medium according to the present invention, if the largest space is allocated to an user data area, the number of blocks to store a space bitmap is Ni (where Ni?2). But if the smallest space is allocated to the user data area, the number of blocks to use is smaller than Ni.

Abstract: A circuit contains a shared memory (12), that is used by a plurality of processing elements (10) that contain cache circuits (102) for caching data from the shared memory (12). The processing elements perform a plurality of cooperating tasks, each task involving caching data from the shared memory (12) and sending cache message traffic. Consistency between cached data for different tasks is maintained by transmission of cache coherence requests via a communication network. Information from cache coherence requests generated for all of said tasks is buffered. One of the processing elements provides an indication signal indicating a current task stage of at least one of the processing elements. Additional cache message traffic is generated adapted dependent on the indication signal and the buffered information from the cache coherence requests. Thus conditions of cache traffic stress may be created to verify operability of the circuit, or cache message traffic may be delayed to avoid stress.

Abstract: Described are techniques for caching. At a first point in time, a first set of data portions currently stored in a first cache of a first data storage system is determined. Each data portion of the first set is located on a first device of the first data storage system. Sent to a second data storage system is first information including information identifying a storage location on the first device for each data portion of the first set. The second data storage system includes a second device that is maintained as a mirror of the first device. The storage location for each data portion of the first set is used to identify a second storage location of the second device corresponding to the storage location. The first information is used to populate a second cache of the second data storage system.

Abstract: A storage device for storing data includes a device configured to store data read or written by a host, a command storage unit configured to store commands transmitted by the host to acquire information relating to the device, a command acquisition unit configured to acquire commands issued to the device when the host requests access to the data stored in the device, and an access determination unit configured to permit the access, if the commands acquired by the command acquisition unit have been stored in the command storage unit.

Abstract: A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded. The value of the most significant bits is output. The value of a neighboring bit of each storage unit is obtained and recorded. The neighboring bit neighbors the most significant bit. The value of the neighboring bits is output.

Abstract: The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed.

Abstract: Storage system arrangements having status information including both copy group summary status information providing a status of a group of the plurality of copy pairs, and detailed status information detailing a status of a copy pair included in the group; and wherein said status management unit monitors the status information of said plurality of copy pairs, wherein the management computer acquires, from the storage apparatus, the copy group summary status information as summary information for a group of the plurality of copy pairs having a failure status for the group, and displays said summary information on said display, if the summary information indicates a normal status, the management computer displays the summary information only; and if the summary information indicates a failure status, the management computer displays, upon receiving selection of said summary information, detailed status information of a copy pair that belongs to the group.

Abstract: A data storage device is disclosed including a non-volatile media having a first and a second plurality of physical locations, the first plurality of physical locations storing user data and the non-volatile media storing first metadata associating each of the first plurality of physical locations with a logical block address (LBA), and a mapping table including a mapping of each LBA to a current physical location. The data storage device further includes control circuitry that reads the first metadata to obtain a first plurality of LBAs, reads the mapping table to determine a current physical location for the first plurality of LBAs, and compares the current physical location of each of the first plurality of LBAs to a corresponding one of the first plurality of physical locations to identify valid user data in the first plurality of physical locations for migration into the second plurality of physical locations.

Abstract: In one implementation, a data set including a plurality of data values having an order is stored at a memory having a plurality of memory locations. Each data value from the data set stored a current memory location of that data value from the plurality of memory locations. Each data value from the data set is periodically moved from the current memory location of that data value from the plurality of memory locations to a next memory location of that data value from the plurality of memory locations. The next memory location of each data value from the plurality of memory locations is the current memory location of that data value from the plurality of memory locations after the moving. The plurality of data values is then provided in the order to a client in response to a request for the data set.

Abstract: An electronic device including a NAND flash memory, an auxiliary memory, and a controller is provided. A code for detecting a read command sequence of the NAND flash memory is stored in the auxiliary memory. During a boot procedure of the electronic device, the controller reads the code from the auxiliary memory and executes the code to obtain the read command sequence of the NAND flash memory, so as to access content stored in the NAND flash memory according to the read command sequence.

Abstract: A multi-processor system is disclosed comprising a first processor, a first memory coupled to the first processor, a second processor, and a shared memory subsystem including a shared memory and a data transfer unit. The first processor is configured to build a data structure in the first memory and to send a direct memory access (DMA) transfer request to the data transfer unit of the shared memory subsystem, the DMA transfer request including an address of the data structure in the first memory. The data transfer unit is configured to retrieve the data structure from the first memory based on the DMA transfer request, to store the data structure in the shared memory, and to send a shared memory pointer to the second processor indicating an address of the data structure in the shared memory.

Abstract: An interface controller of a storage device configured to manage a write cache of the storage device responsive to changes in a voltage supply provided to the storage device. In one implementation, the interface controller reduces the size of the write cache responsive to the voltage supply dropping at or below a first threshold. The interface controller further disables write permissions to the write cache responsive the voltage supply dropping at or below a second threshold, wherein the second threshold is lower in magnitude that the first threshold. The interface controller periodically receives the voltage supply responsive to transmitting sequential requests to a servo firmware of the storage device.

Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.

Abstract: A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management.

Abstract: A Dynamic Random Access Memory (DRAM) controller. The DRAM controller includes receiving a plurality of access requests from a plurality of user interfaces to access one or more DRAM devices. Further, the DRAM controller includes storing the plurality of access requests in a Content Addressable Memory (CAM). Furthermore, the DRAM controller includes updating at least one access request of the plurality of access requests to a Next Access Table. In addition, the DRAM controller includes determining at least one paramount access request of the plurality of access requests by a CAM based decision controller for employing a bypass operation in the CAM based decision controller, based on a plurality of pre-defined conditions. Further, the DRAM controller includes issuing the plurality of access requests to the one or more DRAM devices.

Abstract: Described in detail herein are systems and methods for single instancing blocks of data in a data storage system. For example, the data storage system may include multiple computing devices (e.g., client computing devices) that store primary data. The data storage system may also include a secondary storage computing device, a single instance database, and one or more storage devices that store copies of the primary data (e.g., secondary copies, tertiary copies, etc.). The secondary storage computing device receives blocks of data from the computing devices and accesses the single instance database to determine whether the blocks of data are unique (meaning that no instances of the blocks of data are stored on the storage devices). If a block of data is unique, the single instance database stores it on a storage device. If not, the secondary storage computing device can avoid storing the block of data on the storage devices.