Abstract: A display device including a base layer, a circuit layer, a light emitting device layer, an organic layer, and a touch sensing unit. The base layer includes a display area and a non-display area. A plurality of insulation patterns overlaps the non-display area. The organic layer is disposed on the light emitting device and overlaps the plurality of insulation patterns and the organic light emitting diode. At least a portion of the plurality of touch signal lines overlaps the plurality of insulation patterns.

Abstract: A display device includes a through portion passing through a display layer. The display includes a plurality of scan lines above the substrate and extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels connected to the scan lines and data lines. The data lines include a first data line and a second data line disconnected by the through portion, and a third data line spaced apart from the through portion along the first direction. The first data line is electrically connected with the third data line.

Abstract: A header for a semiconductor package includes: an eyelet having an upper surface and a lower surface; a first metal block molded integrally with the eyelet, protruding at the upper surface, and having a substantially U shape; a first lead sealed in a first through hole penetrating the eyelet; a first substrate having a front surface formed with a first signal pattern electrically connected to the first lead and having a back surface fixed to a first end surface of the first metal block; a second lead sealed in a second through hole penetrating the eyelet; and a second substrate having a front surface formed with a second signal pattern electrically connected to the second lead and having a back surface fixed to a second end surface of the first metal block.

Abstract: An organic light-emitting diode (“OLED”) includes a bottom electrode, a top electrode disposed opposite to the bottom electrode, and an organic layer that is interposed between the bottom electrode and the top electrode and includes a hole-transporting host and an electron-transporting host forming an exciplex and a phosphorescent dopant having a triplet energy which is lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host, and the triplet energy of the exciplex, and a lighting device and a display apparatus including the OLED. Instead of a phosphorescent dopant, the fluorescent dopant having a singlet energy which is lower than the singlet energy of the exciplex may be also used.

Abstract: A light emitting device includes: a base; a first terminal and a second terminal located at a surface of the base; a light emitting element array chip mounted on the base, the light emitting element array chip including: a support substrate, a plurality of first wirings and a plurality of second wirings disposed on the support substrate, and a plurality of light emitting elements, each of the light emitting elements arranged on the first wiring and the second wiring and electrically connected to the first wiring and the second wiring; and a plurality of wires including a first wire connecting the first wiring to the first terminal, and a second wire connecting the second wiring to the second terminal.

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

Abstract: The present disclosure is directed to methods for producing a photovoltaic junction that can include coating a bare junction with a composition. In one embodiment, the composition includes a plurality of quantum dots to create a film; exposing the film to a ligand to create a first layer; coating the first layer with the composition to form a film on the first layer; and exposing the film on the first layer to the ligand to create a second layer.

Abstract: A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

Abstract: A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes.

Abstract: A semiconductor apparatus includes: a system substrate; a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction; a conductive label flexible and arranged on the semiconductor package, the conductive label including: a first adhesive layer contacting the semiconductor package; a thermally-conductive layer attached to the semiconductor package by the first adhesive layer and having a second length in the first horizontal direction greater than the first length; and a second adhesive layer contacting a portion of a surface of the conductive layer, the portion not vertically overlapping the semiconductor package; a thermal interface material (TIM) arranged on the conductive layer to vertically overlap the semiconductor package; and a cover including: a first cover portion vertically overlapping the semiconductor package and contacting the TIM; and a second cover portion to which the thermally-conductive layer is attached by the second adhesive layer.

Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.

Abstract: Disclosed is a low temperature method of fabrication of short-wave infrared (SWIR) detector arrays (FPA) including a readout wafer and absorption layer connected for improved performances. The absorber layer includes a SWIR conversion layer with a GeSn or SiGeSn alloy. A first series of process steps realizes a CMOS processed readout wafer. A buffer layer is transferred on the readout wafer and annealed at temperatures compatible with the CMOS substrate, achieving a high quality crystalline buffer layer. The method assures a temperature profile between the light entrance surface of the buffer layer, and the readout electronics so the annealing temperature remains compatible with the CMOS. The buffer layer is used for further growth of a GeSn or SiGeSn structure to create the conversion layer and achieve the final structure of the SWIR FPA. Also disclosed is a SWIR FPA detector as realized by such method, and SWIR FPA applications.

Abstract: One aspect of the invention relates to a multi-terminal memtransistor. The memtransistor includes a substrate having a first surface and an opposite, second surface, a polycrystalline monolayer film formed of an atomically thin material on the first surface of the substrate, an electrode array having a plurality of electrodes spatial-apart formed on the polycrystalline monolayer film such that each pair of electrodes defines a channel in the polycrystalline monolayer film therebetween, and a gate electrode formed on the second surface of the substrate and capacitively coupled with the channel. The polycrystalline monolayer film contains grains defining a plurality of grain boundaries thereof. The multi-terminal memtransistor operates much like a neuron by performing both memory and information processing, and can be a foundational circuit element for new forms of neuromorphic computing.

Abstract: A method of manufacturing a display apparatus includes preparing a panel with a panel layer displaying images, a first protection film on a first surface of the panel layer with a first adhesion layer, and a second protection film on a second surface of the panel layer with a second adhesion layer, disposing the panel on a stage, cutting the panel on the stage along a closed-curve line to a predetermined depth extending from the second protection film to at least a portion of the first adhesion layer, and separating a first portion of the panel inside the closed-curve line from a second portion of the panel outside the closed-curve line, such that the second portion is removed simultaneously with the entire first protection film according to a first boundary by the line and a second boundary between the panel layer and the first protection film.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: In an illuminance sensor, a slow axis of a first portion comprises a relation of +45° or ?45° in regard to a first polarization direction that is a polarization direction of the a linear polarization plate, a relation of a slow axis of a second portion in regard to the first polarization direction is ?45° or +45° that is opposite in sign to the relation of the slow axis of the first portion in regard to the first polarization direction, and a slow axis of a second quarter-wave plate comprises a relation of +45° or ?45° in regard to a second polarization direction that is a polarization direction of a second linear polarization plate, wherein the relation of the slow axis of the second quarter-wave plate in regard to the second polarization direction is the same with the relation of the slow axis of the first portion in regard to the first polarization direction.

Abstract: A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.

Abstract: A resistance access memory device includes a first electrode, a resistance change layer, formed on the first electrode, comprising a thin film containing BiX13 and and Bi2X2(3-x), and a second electrode formed on the resistance change layer, where X1 is a halogen element selected from the group consisting of F, Cl, Br, I, and combinations thereof, X2 is a chalcogen element selected from the group consisting of S, Se, Te, and combinations thereof, and x is a real number of 0 or more and less than 3.