Abstract: Provided are an organic light-emitting diode (“OLED”) including a bottom electrode, a top electrode disposed opposite to the bottom electrode, and an organic layer that is interposed between the bottom electrode and the top electrode and includes a hole-transporting host and an electron-transporting host forming an exciplex and a phosphorescent dopant having a triplet energy which is lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host, and the triplet energy of the exciplex, and a lighting device and a display apparatus including the OLED. Instead of a phosphorescent dopant, the fluorescent dopant having a singlet energy which is lower than the singlet energy of the exciplex may be also used.

Abstract: The present application provides an organic light emitting diode (OLED) display panel and a package method thereof, the OLED display panel includes a thin film transistor layer, an OLED light emitting layer, and a thin film encapsulation layer, which are sequentially disposed on a substrate; the thin film encapsulation layer includes laminated disposing inorganic encapsulation layers and an organic encapsulation layer; wherein the material forming the organic encapsulation layer is methyl methacrylate-N-isopropyl acrylamide copolymer solution, which is spread on the surface of the inorganic encapsulation layer and after curing, used to form an organic encapsulation layer.

Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.

Abstract: A membrane device includes a trench substrate having trenches and a membrane having wrinkles. The membrane is not bonded to the trenches of the trench substrate but is bonded to the surface of the trench substrate in the shoulders of the trenches. Hills and valleys are alternately arranged in the membrane along the trenches. The membrane device can be used in various applications (for example, sensors) based on variations in the electrical properties of the membrane caused by a change in the shape of the wrinkles (a change in the strain) of the membrane in response to a change in the internal or external environment of the trenches.

Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.

Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.

Abstract: Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps.

Abstract: The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.

Abstract: A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.

Abstract: An image capturing apparatus where a pixel region that includes a photoelectric converter and a peripheral region that includes a transistor are arranged in a substrate is provided. The photoelectric converter is covered with a first silicon nitride layer, a side surface of a gate electrode of the transistor is covered with a side wall that include a second silicon nitride layer, and the first silicon nitride layer has a lower chlorine concentration than the second silicon nitride layer has.

Abstract: A semiconductor structure with cutting depth control and method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, fins protruding from a substrate are formed. Next, source/drain devices are grown on both ends of the fins. Then, an inter-layer dielectric layer crossing the fins and enclosing the source/drain devices is deposited. A metal gate structure enclosed by the inter-layer dielectric layer is formed between the source/drain devices. And then, a replacement operation is performed to replace a portion of the inter-layer dielectric layer with an isolation material, thereby forming an isolation portion that adjoins the metal gate structure and is located between the adjacent source/drain devices. Thereafter, a metal gate cut operation is performed, thereby forming an opening in the metal gate structure and an opening in the isolation portion, and an insulating material is deposited in the openings.

Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.

Abstract: There is provided a method of forming a carbon film on a workpiece, which includes: loading the workpiece into a process chamber; supplying a gas containing a boron-containing gas into the process chamber to form a seed layer composed of a boron-based thin film on a surface of the workpiece; and subsequently, supplying a hydrocarbon-based carbon source gas and a pyrolysis temperature lowering gas containing a halogen element and which lowers a pyrolysis temperature of the hydrocarbon-based carbon source gas into the process chamber, heating the hydrocarbon-based carbon source gas to a temperature lower than the pyrolysis temperature to pyrolyze the hydrocarbon-based carbon source gas, and forming the carbon film on the workpiece by a thermal CVD.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes: forming an auxiliary electrode including: a first conductive layer; and a second conductive layer disposed on the first conductive layer, the second conductive layer having a resistance higher than a resistance of the first conductive layer; forming a first intermediate layer on the auxiliary electrode; exposing the first conductive layer includes forming a first opening in the first intermediate layer and an opening portion in the second conductive layer by removing a portion of the first intermediate layer and a portion of the second conductive layer of the auxiliary electrode; and forming an opposite electrode on the first intermediate layer and the first conductive layer, wherein the opposite electrode is disposed contacting the first conductive layer exposed through the first opening of the first intermediate layer and the opening portion of the second conductive layer.

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.

Abstract: A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

Abstract: A STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a bias voltage controlled perpendicular anisotropy of a recording layer through an interlayer interaction to achieve a lower spin-transfer switching current. The anisotropy modification layer is under an electric field along a perpendicular direction with a proper voltage between a digital line and a bit line from a control circuitry, accordingly, the energy switch barrier is reduced in the spin-transfer recording while maintaining a high thermal stability and a good retention.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes: forming an auxiliary electrode including: a first conductive layer; and a second conductive layer disposed on the first conductive layer, the second conductive layer having a resistance higher than a resistance of the first conductive layer; forming a first intermediate layer on the auxiliary electrode; exposing the first conductive layer includes forming a first opening in the first intermediate layer and an opening portion in the second conductive layer by removing a portion of the first intermediate layer and a portion of the second conductive layer of the auxiliary electrode; and forming an opposite electrode on the first intermediate layer and the first conductive layer, wherein the opposite electrode is disposed contacting the first conductive layer exposed through the first opening of the first intermediate layer and the opening portion of the second conductive layer.

Abstract: A diode and logic gate comprising cells is disclosed. A method of making the diode and logic gate comprising cells is disclosed.