Abstract: A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

Abstract: A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.

Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of SixGe1-x, where 0?x?0.3, the first semiconductor layer is made of SiyGe1-y, where 0.45?y?1.0, and the second semiconductor layer is made of SizGe1-z, where 0?z?0.3.

Abstract: The present disclosure provides a photodiode, a display substrate, and manufacturing methods thereof, and a display device. The method for manufacturing the photodiode includes: forming a semiconductor material layer on a base substrate in a non-display region of a display substrate, the semiconductor material layer including a first contact area, a second contact area, and a semiconductor area sandwiched therebetween; processing the first contact area of the semiconductor material layer to form a first contact electrode; processing portions of the semiconductor material layer and the second contact area away from the base substrate in the semiconductor area, to form a first semiconductor layer and a second semiconductor layer stacked, the second semiconductor layer being located on a side of the first semiconductor layer away from the base substrate; and processing the second semiconductor layer in the second contact area to form a second contact electrode.

Abstract: In an illuminance sensor, a slow axis of a first quarter-wave plate has a relation of +45° or ?45° in regard to a polarization direction of a first linear polarization plate; a relation of a slow axis of a first portion of a second quarter-wave plate in regard to a polarization direction of a second linear polarization plate is the same with relation of the slow axis of the first quarter-wave plate in regard to the polarization direction of the first linear polarization plate, that is, +45° or ?45°; and a relation of a slow axis of a second portion of the second quarter plate in regard to the polarization direction of the second linear polarization plate is ?45° or +45° that is opposite in sign to the relation of the slow axis of the first quarter-plate in regard to the polarization direction of the first linear polarization plate.

Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.

Abstract: The present disclosure is directed to photovoltaic junctions and methods for producing the same. Embodiments of the disclosure may be incorporated in various devices for applications such as solar cells and light detectors and may demonstrate advantages compared to standard materials used for photovoltaic junctions such as silica. An example embodiment of the disclosure includes a photovoltaic junction, the junction including a light absorbing material, an electron acceptor for shuttling electrons, and a metallic contact. In general, embodiments of the disclosure as disclosed herein include photovoltaic junctions which provide absorption across one or more wavelengths in the range from about 200 nm to about 1000 nm, or from near IR (NIR) to ultra-violet (UV). Generally, these embodiments include a multi-layered light absorbing material that can be formed from quantum dots that are successively deposited on the surface of an electron acceptor (e.g., a semiconductor).

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

Abstract: Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described.

Abstract: A photovoltaic device (10) comprising a photoactive body between two electrodes (contact 1, contact 2). The body comprises semiconductor particles (24) embedded in a semiconductor matrix (22). The particles and matrix are electronically or optically coupled so that charge carriers generated in the particles are transferred directly or indirectly to the matrix. The matrix transports positive charge carriers to one of the electrodes and negative charge carriers to the other electrode. The particles are configured so that they do not form a charge carrier transport network to either of the electrodes and so perform the function of charge carrier generation but not charge carrier transport.

Abstract: A display device including a base layer, a circuit layer, a light emitting device layer, an organic layer, and a touch sensing unit. The base layer includes a display area and a non-display area. A plurality of insulation patterns overlaps the non-display area. The organic layer is disposed on the light emitting device and overlaps the plurality of insulation patterns and the organic light emitting diode. At least a portion of the plurality of touch signal lines overlaps the plurality of insulation patterns.

Abstract: A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

Abstract: A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes.

Abstract: Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.

Abstract: A display substrate and a display device. The display substrate comprises a first sub-pixel (111), a second sub-pixel (112), and a first spacer (0101). A line connecting the center (C1) of the first sub-pixel (111) and the center (C2) of the second sub-pixel (112) is a center line (CL1); the center line (CL1) is not perpendicular to a first direction (X); the first direction (X) is at least one of the row direction or the column direction. The first spacer (0101) is disposed between the first sub-pixel (111) and the second sub-pixel (112), and the extension direction (E01) of first spacer (0101) between the first sub-pixel (111) and the second sub-pixel (112) is not perpendicular to the first direction (X). Therefore, the display substrate can improve the different viewing angle color cast and improve the display quality.

Abstract: A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a substrate including a separation area and a plurality of pixel formed over the substrate. The separation area is formed between adjacent pixels, and a plurality of through holes are respectively defined by a plurality of surrounding inner surfaces of the separation area, and wherein each of the inner surfaces passes through the substrate. The display device also includes an encapsulation layer formed over the substrate and covering the inner surfaces of the separation area.

Abstract: Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fin-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fin-FET transistors disposed in the dielectric layer.

Abstract: A display panel includes a base layer, a first thin film transistor disposed on the base layer and including a silicon semiconductor pattern, a first control electrode is spaced apart from the silicon semiconductor pattern. A first input electrode is connected to a first side of the silicon semiconductor pattern. A first output electrode is connected to a second side of the silicon semiconductor pattern. The display panel includes a second thin film transistor. An organic light emitting diode includes a first electrode connected to the first thin film transistor, a second electrode, and an emission layer. A first insulating layer includes openings exposing the first side and the second side of the silicon semiconductor pattern, respectively. The first input electrode and the first output electrode are positioned in the openings, respectively.

Abstract: A display device includes a through portion passing through a display layer. The display includes a plurality of scan lines above the substrate and extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels connected to the scan lines and data lines. The data lines include a first data line and a second data line disconnected by the through portion, and a third data line spaced apart from the through portion along the first direction. The first data line is electrically connected with the third data line.