Abstract: A method for making a semiconductor device may include forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an active device layer on the superlattice comprising at least one active semiconductor device.

Abstract: A method of manufacturing a display apparatus includes preparing a panel with a panel layer displaying images, a first protection film on a first surface of the panel layer with a first adhesion layer, and a second protection film on a second surface of the panel layer with a second adhesion layer, disposing the panel on a stage, cutting the panel on the stage along a closed-curve line to a predetermined depth extending from the second protection film to at least a portion of the first adhesion layer, and separating a first portion of the panel inside the closed-curve line from a second portion of the panel outside the closed-curve line, such that the second portion is removed simultaneously with the entire first protection film according to a first boundary by the line and a second boundary between the panel layer and the first protection film.

Abstract: The photodetector is formed in a silicon carbide body formed by a first epitaxial layer of an N type and a second epitaxial layer of a P type. The first and second epitaxial layers are arranged on each other and form a body surface including a projecting portion, a sloped lateral portion, and an edge portion. An insulating edge region extends over the sloped lateral portion and the edge portion. An anode region is formed by the second epitaxial layer and is delimited by the projecting portion and by the sloped lateral portion. The first epitaxial layer forms a cathode region underneath the anode region. A buried region of an N type, with a higher doping level than the first epitaxial layer, extends between the anode and cathode regions, underneath the projecting portion, at a distance from the sloped lateral portion as well as from the edge region.

Abstract: A semiconductor package includes a die, through insulator vias, an encapsulant, and a pair of metallization layers. The through insulator vias are disposed beside the die. The encapsulant wraps the die and the through insulator vias. The pair of metallization layers is disposed on opposite sides of the encapsulant. One end of each through insulator via contacts one of the metallization layers and the other end of each through insulator via contacts the other metallization layer. The through insulator vias form at least one photonic crystal structure. A pair of the through insulator vias is separated along a first direction by a channel filled by the encapsulant. A width of the channel along the first direction is larger than a pitch of the photonic crystal structure along the first direction.

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

Abstract: A method for removing a resist layer is provided. A resist layer is formed with a material comprising a metal oxide core with organic ligands. A chlorine-containing compound or a methyl group-containing compound is globally applied onto the resist layer to allow the chlorine-containing compound or the methyl group-containing compound to perform a ligand exchange process with the resist layer so as to remove the resist layer through sublimation.

Abstract: A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer.

Abstract: A method for etching a poly-granular metal-based film includes providing a flow of a background gas in a plasma etching chamber containing a semiconductor structure including the poly-granular metal-based film formed over a substrate with a mask patterned over the poly-granular metal-based film. The method also includes applying a source power to generate a background plasma from the background gas, and providing a flow of a modifying gas while maintaining the flow of the background gas to generate a modifying plasma that produces a surface modification region with a substantially uniform depth in the top surface of the poly-granular metal-based film exposed by the mask. The method further includes stopping the flow of the modifying gas while maintaining the flow of the background gas, and applying a biasing power to the substrate to remove the surface modification region.

Abstract: Disclosed herein is an organic light emitting diode display, including a substrate, a first thin film transistor including a first active pattern on the substrate and a first gate electrode on the first active pattern, a data wire on the first gate electrode, a first interlayer insulating layer between the first gate electrode and the data wire, a second interlayer insulating layer positioned the first interlayer insulating layer and the data wire, and an organic light emitting diode positioned on the data wire and connected to the first active pattern.

Abstract: A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features.

Abstract: An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.

Abstract: A device substrate comprising a substrate, a first pad, a second pad, a plurality of first power lines, a plurality of second power lines, and a plurality of control units is provided. The first pad is disposed on the first side of the device substrate. The second pad is disposed on the second side of the device substrate. The second side is opposite the first side. The first power lines are electrically connected to the first pad. The second power lines are electrically connected to the second pad. The control unit is electrically connected to at least one of the first power line and the second power line. The first pad does not overlap the second pad in a first direction perpendicular to the first side or in a second direction perpendicular to the second side. A display panel is also provided. A tiled display is also provided.

Abstract: According to one aspect of the technique described herein, there is provided a technique including: forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes sequentially performing: (a) supplying source gas to a substrate accommodated in a reaction tube; (b) exhausting the source gas remaining in the reaction tube through an exhaust pipe connected to the reaction tube; (c) supplying a reactive gas reacting with the source gas to the substrate; and (d) exhausting the reactive gas remaining in the reaction tube through the exhaust pipe, wherein at least in (a) and (c), a temperature of the reaction tube is set to a first temperature lower than a thermal decomposition temperature of the source gas and higher than a condensation temperature of the source gas and a temperature of the exhaust pipe is set to a second temperature equal to or higher than the first temperature.

Abstract: Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.

Abstract: Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described.

Abstract: The present disclosure provides a thin film transistor and a fabrication method thereof, and an array substrate. The thin film transistor formed on a base substrate, the thin film transistor includes: an active layer; a first signal metal layer, provided on a surface of the active layer facing the base substrate; a second signal metal layer, provided on a surface of the active layer facing away from the first signal metal layer, wherein, the active layer includes a conductive channel formation region, and the second signal metal layer does not cover the conductive channel formation region of the active layer.

Abstract: A method is disclosed for promoting the formation of uniform platelets in a monocrystalline semiconductor donor substrate by irradiating the monocrystalline semiconductor donor substrate with light. The photon-absorption assisted platelet formation process leads to uniformly distributed platelets with minimum built-in stress that promote the formation a well-defined cleave-plane in the subsequent layer transfer process.

Abstract: In an embodiment, a package includes a first package structure including a first integrated circuit die having an active side and a back-side, the active side including die connectors, a second integrated circuit die adjacent the first integrated circuit die, the second integrated circuit die having an active side and a back-side, the active side including die connectors, a routing die including die connectors bonded to the active sides of the first integrated circuit die and the second integrated circuit die, the routing die electrically coupling the first integrated circuit die to the second integrated circuit die, an encapsulant encapsulating the first integrated circuit die, the second integrated circuit die, and the routing die, and a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the second integrated circuit die.

Abstract: A method for manufacturing a light emitting device includes: providing a wafer that includes, successively from an upper face side, an electrode structure that includes multilayer wiring, a semiconductor layer electrically connected to the electrode structure, and a growth substrate; bonding the wafer to a support substrate; exposing the semiconductor layer by removing the growth substrate from the wafer; separating the semiconductor layer into a plurality of light emitting elements, which comprises forming grooves on a semiconductor layer side surface of the wafer; and forming a phosphor layer having protrusions and recesses at a surface thereof such that the phosphor layer covers surfaces of the light emitting elements, which comprises: forming a coating film on surfaces of the light emitting elements by applying a slurry comprising phosphor particles contained in a solvent, and vaporizing the solvent in the coating film to form the phosphor layer.

Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.