Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

Abstract: A first gate structure straddles one end of a staircase fin stack that contains a first semiconductor material fin, an insulator fin, and a second semiconductor material fin, a second gate structure straddles a portion of the staircase fin stack, a third gate structure straddles another end of the staircase fin stack, and a fourth gate structure straddles a portion of only the first semiconductor fin. A first contact structure is between the first and second gate structures, a second contact structure is between the second and third gate structures, and a third contact structure is between the third and fourth gate structures. The first contact structure has a contact metal that contacts the first and second semiconductor material fins. The second contact structure has a contact metal that contacts only the second semiconductor material fin, and the third contact structure has a contact metal that contacts only the first semiconductor fin.

Abstract: Variation in the electrical characteristics of transistors is minimized and reliability of the transistors is improved. A display device includes a pixel portion 104 and a driver circuit portion 106 outside the pixel portion. The pixel portion includes a pixel transistor, a first insulating layer 122 which covers the pixel transistor and includes an inorganic material, a second insulating layer 124 which is over the first insulating layer and includes an organic material, and a third insulating layer 128 which is over the second insulating layer and includes an inorganic material. The driver circuit portion includes a driving transistor for supplying a signal to the pixel transistor, and the first insulating layer covering the driving transistor. The second insulating layer is not formed in the driver circuit portion.

Abstract: A photoresponse device comprising a nanocomposite photoactive material is provided. The photoactive layer comprises a nanocomposite material of metal oxide nanoparticles dispersed within a photosensitizing organic semiconductor formed on a substrate. Methods of characterizing the nanocomposites are provided and demonstrate commercially relevant electrical and photodetection properties, particularly the ability to operate as a photodiode, photoconductor or photocapacitor. An economical process for preparing the nanocomposite and the photoresponse device is also provided as well as applications.

Abstract: A display device includes a display panel configured to display an image, and a protection film coupled to a lower portion of the display panel. The protection film includes a support film contacting the display panel and a stress control layer below the support film, and the stress control layer includes a plurality of nanobeads.

Abstract: The present invention discloses a photo-detector comprising: an n-type photon absorbing layer of a first energy bandgap; a middle barrier layer, an intermediate layer is a semiconductor structure; and a contact layer of a third energy bandgap, wherein the layer materials are selected such that the first energy bandgap of the photon absorbing layer is narrower than that of said middle barrier layer; wherein the material composition and thickness of said intermediate layer are selected such that the valence band of the intermediate layer lies above the valence band in the barrier layer to create an efficient trapping and transfer of minority carriers from the barrier layer to the contact layer such that a tunnel current through the barrier layer from the contact layer to the photon absorbing layer is less than a dark current in the photo-detector and the dark current from the photon-absorbing layer to said middle barrier layer is essentially diffusion limited and is due to the unimpeded flow of minority carrier

Abstract: A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad.

Abstract: Provided are an organic light emitting display (OLED) device and method for manufacturing the same. The OLED device includes: a plurality of gate lines in one direction on a substrate, a plurality of light-shielding patterns corresponding to at least parts of peripheries of the respective pixel regions on the substrate, the light-shielding patterns spaced apart from the gate lines, at least one insulating film covering the substrate, the gate lines, and the light-shielding patterns, a plurality of data lines in another direction crossing the gate lines on the insulating film to define the pixel areas, a passivation film covering the insulating film and the data lines, a plurality of color filters in the pixel areas on the passivation film, an over-coating film evenly covering the passivation film and covering the color filters, and a plurality of organic light emitting elements in the pixel areas on the over-coating film.

Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

Abstract: A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.

Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

Abstract: An organic EL display device includes lower electrodes each provided for each of pixels, a bank layer formed so as to cover the peripheries of the lower electrodes and including bank openings through each of which a portion of the lower electrode is exposed, a light-emitting layer, an organic layer including portions each formed in the bank opening, a first barrier layer covering the organic layer, a second barrier layer covering the first barrier layer, an intermediate layer located at the edges of the bank openings, and light reflection films each provided under the lower electrode for each of the pixels. A first region where the intermediate layer is present when the pixel is viewed in a plan view includes, above or under the intermediate layer, a different layer structure from that of a second region inside the first region.

Abstract: An organic light-emitting diode (OLED) display, electronic device including the same and method of manufacturing the OLED display are disclosed. In one aspect, the OLED display includes a first plastic layer, a first barrier layer formed over the first plastic layer and a first intermediate layer formed over the first barrier layer. The OLED display also includes a second plastic layer formed over the first intermediate layer, a second intermediate layer formed over the second plastic layer and a second barrier layer formed over the second intermediate layer. The OLED display further includes an OLED layer formed over the second barrier layer and a thin-film encapsulation layer encapsulating the OLED layer.

Abstract: Embodiments of the invention provide a conductive structure, a thin film transistor, an array substrate, and a display device. The conductive structure comprises a copper layer formed of copper or copper alloy; a blocking layer for preventing copper ions of the copper layer from diffusing outward; and a diffusion prevention layer for preventing exterior ions from diffusing to the copper layer and disposed between the copper layer and the blocking layer. The multilayer conductive structure according to an embodiment of the invention can prevent exterior ions from diffusing into a copper layer and prevent copper ions from diffusing outward to reduce ions diffusion that adversely impacts the electricity performance and chemical corrosion resistance of the copper metal layer, and meanwhile can enhance adhesiveness of the conductive structure, which may be helpful for etching/patterning of the multilayer conductive structure.

Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

Abstract: A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate includes, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.

Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

Abstract: A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module includes a thyristor having terminals and a gate, and a diode coupled in antiparallel to the terminals of the thyristor. Each module is sized to share a saturation current with neighboring modules when an electrostatic discharge current is received. A resistive network couples modules between two terminals. A triggering circuit includes a common triggering output that is coupled to the gate of the thyristor of each module and a common buried semiconductor layer contacts each module.

Abstract: In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N? type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.