Abstract: Disclosed is a quantum dot light emitting device including a ligand-substituted quantum dot light emitting layer with a polymer having amine groups. The introduction of the ligand-substituted quantum dot light emitting layer with a polymer having amine groups changes the energy level of an electron transport layer and enables control over the charge injection properties of the device so that the flow of electrons can be controlled. In addition, the ligand substitution is effective in removing oleic acid as a stabilizer of quantum dots to prevent an increase in driving voltage caused by the introduction of the additional material, achieving markedly improved efficiency of the device. Also disclosed is a method for fabricating the quantum dot light emitting device.

Abstract: Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.

Abstract: An organic electroluminescent device containing a cathode, an anode, and one or more organic layers containing plural light emitting materials between the cathode and the anode, wherein the organic electroluminescent device is a multiple wavelength light emitting organic electroluminescent device emitting light from the plural light emitting materials, and which is designed so that light that has the shortest wavelength contains delayed fluorescent light can improve light emission efficiency of a short wavelength light and color tone and has a large degree of freedom in design and a simple structure.

Abstract: A method of manufacturing a display apparatus includes preparing a panel with a panel layer displaying images, a first protection film on a first surface of the panel layer with a first adhesion layer, and a second protection film on a second surface of the panel layer with a second adhesion layer, disposing the panel on a stage, cutting the panel on the stage along a closed-curve line to a predetermined depth extending from the second protection film to at least a portion of the first adhesion layer, and separating a first portion of the panel inside the closed-curve line from a second portion of the panel outside the closed-curve line, such that the second portion is removed simultaneously with the entire first protection film according to a first boundary by the line and a second boundary between the panel layer and the first protection film.

Abstract: Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps.

Abstract: The present disclosure relates to a semiconductor light emitting device, comprising: a plurality of semiconductor layers that grows sequentially on a growth substrate, with the plurality of semiconductor layers including a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer, generating a light with a first wavelength via electron-hole recombination; a first electrode, supplying either electrons or holes to the plurality of semiconductor layers; a second electrode, supplying, to the plurality of semiconductor layers, electrons if the holes are supplied by the first electrode, or holes if the electrons are supplied by the first electrode; a phosphor part provided over the first semiconductor layer on the side of the growth substrate, converting the light with the first wavelength generated in the active layer i

Abstract: A chemical mechanical polishing (CMP) method includes preparing a polishing pad, determining a first load to be applied to a conditioning disk during conditioning of the polishing pad and a first indentation depth at which tips of the conditioning disk are inserted into the polishing pad when the first load is applied to the conditioning disk, preparing a conditioning disk, and positioning the conditioning disk on the polishing pad and conditioning a surface of the polishing pad by using the conditioning disk while applying the first load to the conditioning disk.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

Abstract: The invention relates to a method for manufacturing a Josephson junction comprising a step for providing a substrate, extending along a longitudinal direction, a step for depositing a superconducting layer on the substrate so that this layer extends from the substrate in a transverse direction, perpendicular to the longitudinal direction, and a step for irradiation of ions in a central area of the layer defined in the longitudinal direction, the method being characterized in that it includes, prior to the irradiation step, a step for removing a portion of the central area of the superconducting layer so as to delimit a set of areas of the superconducting layer aligned in the longitudinal direction including the central area and two lateral areas.

Abstract: To provide a field-effect transistor, containing: a substrate; a protective layer; a gate insulating layer formed between the substrate and the protective layer; a source electrode and a drain electrode, which are formed to be in contact with the gate insulating layer; a semiconductor layer, which is formed at least between the source electrode and the drain electrode, and is in contact with the gate insulating layer, the source electrode, and the drain electrode; and a gate electrode, which is formed at an opposite side to the side where the semiconductor layer is provided, with the gate insulating layer being between the gate electrode and the semiconductor layer, and is in contact with the gate insulating layer, wherein the protective layer contains a metal oxide composite, which contains at least Si and alkaline earth metal.

Abstract: A Metal-Insulator-Metal type capacitor structure (1) comprising a substrate (2), a first electrically insulating layer (14) placed on the substrate (2), a lower electrode (6) placed on the first insulating layer (14), a layer of structured metal (12) comprising a plurality of pores disposed on the lower electrode (6), a MIM capacitor (4) comprising a first conductive layer (18) placed on the structured metal layer (12) in contact with the lower electrode (6) and inside the pores, a dielectric layer (20) covering the first conductive layer (18), a second conductive layer (24) covering the dielectric layer (20) in contact with an upper electrode (8) placed on the MIM capacitor (4) and a second electrically insulating layer (16) placed on the upper electrode (8).

Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.

Abstract: Disclosed herein is an organic light emitting diode display, including a substrate, a first thin film transistor including a first active pattern on the substrate and a first gate electrode on the first active pattern, a data wire on the first gate electrode, a first interlayer insulating layer between the first gate electrode and the data wire, a second interlayer insulating layer positioned the first interlayer insulating layer and the data wire, and an organic light emitting diode positioned on the data wire and connected to the first active pattern.

Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

Abstract: A display device includes a through portion passing through a display layer. The display includes a plurality of scan lines above the substrate and extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels connected to the scan lines and data lines. The data lines include a first data line and a second data line disconnected by the through portion, and a third data line spaced apart from the through portion along the first direction. The first data line is electrically connected with the third data line.

Abstract: Disclosed are a substrate bonding apparatus and a method of manufacturing a semiconductor device. The substrate bonding apparatus comprises vacuum pumps, a first chuck engaged with the vacuum pumps and adsorbing a first substrate at vacuum pressure of the vacuum pumps, and a pushing unit penetrating a center of the first chuck and pushing the first substrate away from the first chuck. The first chuck comprises adsorption sectors providing different vacuum pressures in an azimuth direction to the first substrate.

Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

Abstract: The present disclosure provides an OLED substrate, a manufacturing method thereof, and a display device. The OLED substrate comprises: a base substrate; a source-drain metal extending portion arranged on the base substrate; a passivation layer having via holes at positions corresponding to cathode contact regions in a peripheral area; an anode metal extending portion being electrically connected with the source-drain metal extending portion through the via holes; a pixel definition layer having first patterns at positions corresponding to a display area, each having a protrusion portion and a groove portion; the pixel definition layer having second patterns at positions corresponding to the cathode contact regions, each having a protrusion portion and a groove portion. The protrusion portion of the first pattern corresponds to the groove portion of the second pattern, and the groove portion of the first pattern corresponds to the protrusion portion of the second pattern.

Abstract: A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.

Abstract: Provided is a display device and a manufacturing method of the same. The display device includes: a base substrate having a top surface and a side surface, a display region over the top surface, a terminal over the top surface and between the display region and the side surface, the terminal being electrically connected to the display region, and an anisotropic conductive film over the terminal. An edge portion of the anisotropic conductive film is spaced from the side surface, and its distance is equal to or larger than 10 ?m and equal to or smaller than 1 mm.