Patents Examined by Christopher Young
  • Reflective layer-equipped substrate for EUV lithography, reflective mask blank for EUV lithography, reflective mask for EUV lithography, and process for production of the reflective layer-equipped substrate
    Patent number: 8993201
    Abstract: Provided are an EUV mask blank in which deterioration in reflectivity due to oxidation of a Ru protective layer is prevented, a reflective layer-equipped substrate to be used for producing the EUV mask blank, and a process for producing the reflective layer-equipped substrate. A reflective layer-equipped substrate for EUV lithography comprising a substrate, and a reflective layer for reflecting EUV light and a protective layer for protecting the reflective layer, formed in this order on the substrate, wherein the reflective layer is a Mo/Si multilayer reflective film, the protective layer is a Ru layer or a Ru compound layer, and an intermediate layer containing from 0.5 to 25 at % of nitrogen and from 75 to 99.5 at % of Si is formed between the reflective layer and the protective layer.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: March 31, 2015
    Assignee: Asahi Glass Company, Limited
    Inventors: Masaki Mikami, Mitsuhiko Komakine, Yoshiaki Ikuta
  • Method for generating mask pattern
    Patent number: 8986912
    Abstract: A method for generating, via a computer, a mask pattern to be used for an exposure apparatus that exposes an image of the mask pattern on a substrate by irradiating a mask includes obtaining data of a main pattern to be formed on the substrate, and data of a pattern of a lower layer of a layer to which the main pattern is transferred, setting a generation condition for an auxiliary pattern with respect to the main pattern using data of the pattern of the lower layer, determining the auxiliary pattern using the generation condition, and generating data of the mask pattern including the main pattern and the determined auxiliary pattern.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Gyoda
  • Optical member for EUV lithography
    Patent number: 8986910
    Abstract: There are provided an EUV optical member, in which deterioration in the reflectivity due to oxidation of the Ru protective layer is prevented, a functional film-equipped substrate to be employed for production of the EUV optical member. A reflective layer-equipped substrate for EUV lithography comprising a substrate, and a reflective layer for reflecting EUV light and a protective layer for protecting the reflective layer, formed in this order on the substrate, wherein the reflective layer is a Mo/Si multilayer reflective film, the protective layer has a three-layer structure wherein a first layer made of a Ru layer or a Ru compound layer, a second layer made of a Mo layer and a third layer made of a Ru layer or a Ru compound layer are laminated in this order on the reflective layer.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 24, 2015
    Assignee: Asahi Glass Company, Limited
    Inventor: Masaki Mikami
  • Method and apparatus for inspecting a mask substrate for defects, method of manufacturing a photomask, and method of manufacturing a semiconductor device
    Patent number: 8986913
    Abstract: According to one embodiment, a method of inspecting a mask substrate for defects, includes acquiring a defocus image of a partial region of a mask substrate using a dark-field optical system, acquiring a just-focus image of the partial region using the dark-field optical system, generating a set composed of first signals obtained from the defocus image and having signal intensities equal to or higher than a first threshold value, excluding, from the set, the first signals pertaining to parts in which signal intensities of signals obtained from the just-focus image are equal to or higher than a second threshold value, determining an inspection threshold value for signal intensities, on the basis of the first signals not excluded from, and remaining in, the sea.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignees: Kabushiki Kaisha Toshiba, Dai Nippon Printing Co., Ltd.
    Inventors: Takeshi Yamane, Tsuneo Terasawa
  • Binary photomask blank and binary photomask making method
    Patent number: 8980503
    Abstract: A binary photomask blank has on a transparent substrate a light-shielding film including substrate-side and surface-side compositionally graded layers, having a thickness of 35-60 nm, and composed of a silicon base material containing a transition metal and N and/or O. The substrate-side compositionally graded layer has a thickness of 10-58.5 nm , and a N+O content of 25-40 at % at its lower surface and 10-23 at % at its upper surface. The surface-side compositionally graded layer has a thickness of 1.5-8 nm, and a N+O content of 10-45 at % at its lower surface and 45-55 at % at its upper surface.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 17, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Hiroki Yoshikawa, Yukio Inazuki, Kazuhiro Nishikawa, Hideo Kaneko
  • Reflective extreme ultraviolet mask and method of manufacturing the same
    Patent number: 8968969
    Abstract: A reflective extreme ultraviolet mask includes a mask substrate having an exposing region and a peripheral region, the mask substrate including a light-scattering portion in the peripheral region, a reflective layer on an upper surface of the mask substrate, the reflective layer having a first opening exposing the light-scattering portion, and an absorbing layer pattern on the reflective layer, the absorbing layer pattern having a second opening in light communication with the first opening.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Geun Kim, Dong-Wan Kim, Dong-Gun Lee, Seong-Sue Kim
  • Methods for controlling defects for extreme ultraviolet lithography (EUVL) photomask substrate
    Patent number: 8962224
    Abstract: Methods for providing a silicon layer on a photomask substrate surface with minimum defeats for fabricating film stack thereon for EUVL applications are provided. In one embodiment, a method for forming a silicon layer on a photomask substrate includes performing an oxidation process to form a silicon oxide layer on a surface of a first substrate wherein the first substrate comprises a crystalline silicon material, performing an ion implantation process to define a cleavage plane in the first substrate, and bonding the silicon oxide layer to a surface of a second substrate, wherein the second substrate is a quartz photomask.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Ajay Kumar, Omkaram Nalamasu
  • Mask and method of forming pattern by using the same
    Patent number: 8962221
    Abstract: A mask includes a substrate, at least a first strip pattern, at least a second strip pattern and an assist pattern. A width of the second strip pattern is substantially larger than a width of the first strip pattern. The assist pattern is disposed in the second strip pattern neighboring the first strip pattern, and the assist pattern does not overlap a center line of the second strip pattern.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventor: Yu-Shiang Yang
  • Exposure tolerance estimation method and method for manufacturing semiconductor device
    Patent number: 8956791
    Abstract: According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Yamane, Kazuyuki Masukawa, Yasunobu Kai
  • Resist protective film-forming composition and patterning process
    Patent number: 8951712
    Abstract: A pattern is printed by forming a photoresist layer on a wafer, forming a protective film thereon, exposure, and development. The protective film is formed from a composition comprising a copolymer comprising recurring units derived from a styrene, indene, benzofuran or benzothiophene monomer having 1,1,1,3,3,3-hexafluoro-2-propanol, and recurring units derived from a styrene, vinylnaphthalene, indene, benzofuran, benzothiophene, stilbene, styrylnaphthalene or dinaphthylethylene monomer and an ether solvent.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: February 10, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Jun Hatakeyama
  • Method for forming pattern and method for producing original lithography mask
    Patent number: 8951698
    Abstract: A method forming a pattern includes a process in which self-assembly material is formed on the substrate where on which a fiducial mark is formed, and the self-assembly material is separated in micro phase to form a self-assembled pattern. The position error from a predetermined formation position of the self-assembled pattern is measured on the basis of the fiducial mark, and a pattern for an alignment as well as a peripheral circuit pattern are formed on the substrate. The formation position of at least one pattern among the pattern for alignment and peripheral circuit pattern is corrected using the position error.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Rikiya Taniguchi, Hideaki Sakurai, Shinichi Ito
  • Method for creating mask data, program, information processing apparatus, and method for manufacturing mask
    Patent number: 8945801
    Abstract: Data regarding a first corrected patterns on a single cell corrected such that an evaluation value of a pattern formed on a substrate after an image of a pattern of the single cell is projected onto a resist on the substrate and the resist is developed is obtained for each of a plurality of cells, a first evaluation value obtained by evaluating a projected image of the first corrected pattern on the single cell generated by the projection system is obtained for each of the cells, a second evaluation value obtained by, when the cells are arranged adjacent to one another, evaluating the projected images of the first corrected patterns on the cells is calculated, and creating a second corrected pattern by correcting the first corrected patterns on the cells arranged adjacent to one another such that the second evaluation value becomes close to the first evaluation value.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryo Nakayama, Tadashi Arai
  • Smart subfield method for E-beam lithography
    Patent number: 8945803
    Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen, Cheng-Hung Chen, Shih-Chi Wang, Nian-Fuh Cheng, Chia-Chi Lin
  • Method of preparing a pattern, method of forming a mask set, device manufacturing method and computer program
    Patent number: 8945800
    Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 3, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Tsann-Bim Chiou, Mircea Dusa, Alek Chi-Heng Chen
  • System and method for test pattern for lithography process
    Patent number: 8921013
    Abstract: A lithographic mask reticle includes a first mask region having a first mask pattern configured for use in fabrication of electronic circuit structures, and a second mask region having a second mask pattern configured for use in fabrication of test structures. The second mask pattern includes all categories of structural patterns containing in the first mask pattern.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Chi-Yuan Hung, Bin Zhang, Ze Xi Deng, Li Guo Zhang
  • Methods involving color-aware retargeting of individual decomposed patterns when designing masks to be used in multiple patterning processes
    Patent number: 8921016
    Abstract: One illustrative method disclosed herein includes the steps of decomposing an initial overall target exposure pattern into at least a first decomposed sub-target pattern and a second decomposed sub-target pattern, performing first and second retargeting processes on the first and second decomposed sub-target patterns while using the other sub-target pattern as a reference layer, respectively, to thereby define retargeted first and second decomposed sub-target patterns, respectively, and, after performing the first and second retargeting processes, performing at least one process operation to determine if each of the retargeted first decomposed sub-target pattern and the retargeted second decomposed sub-target pattern is in compliance with at least one design rule.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chidambaram G. Kallingal, YuYang Sun
  • Multilayer substrate, manufacturing method for multilayer substrate, and quality control method for multilayer substrate
    Patent number: 8921017
    Abstract: The present invention relates to a multilayer substrate containing a substrate and a multilayer film provided on the substrate, in which a concave or convex fiducial mark that indicates a fiducial position of the multilayer substrate is formed on the surface of the multilayer film on the opposite side to the side of the substrate; and a material of at least a part of the surface of the fiducial mark is different from a material of a most superficial layer of the multilayer film on the opposite side to the side of the substrate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: December 30, 2014
    Assignee: Asahi Glass Company, Limited
    Inventors: Yuzo Okamura, Yoshiaki Ikuta
  • Reflecting mask blank, method for manufacturing reflective mask blank and method for quality control for reflective mask blank
    Patent number: 8916316
    Abstract: The present invention relates to a reflective mask blank containing in this order, a substrate, a multilayer reflective film that reflects exposure light, and an absorber layer that absorbs the exposure light, in which the reflective mask blank further contains a fiducial mark indicating a reference position of the multilayer reflective film, which is formed in a concave shape or in a convex shape on a surface of the multilayer reflective film or on a surface of one layer formed between the multilayer reflective film and the absorber layer, and the fiducial mark is formed so as to have a reflectivity different from an area surrounding the fiducial mark with respect to a light with a prescribed wavelength and is transferred to a layer formed on the fiducial mark.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 23, 2014
    Assignee: Asahi Glass Company, Limited
    Inventors: Yuzo Okamura, Yoshiaki Ikuta
  • Method for fracturing and forming a pattern using shaped beam charged particle beam lithography
    Patent number: 8916315
    Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a plurality of circular or nearly-circular shaped beam shots can form a non-circular pattern on a surface. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming non-circular patterns on a surface using a plurality of circular or nearly-circular shaped beam shots is also disclosed.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: December 23, 2014
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Michael Tucker
  • Developer and patterning process
    Patent number: 8911929
    Abstract: An aqueous solution containing 0.1-10 wt % of a guanidine is a useful developer for photosensitive resist materials. A resist pattern is formed by applying a chemically amplified positive resist composition onto a substrate to form a coating, baking, exposing the coating to high-energy radiation, and developing the exposed coating in a guanidine-containing aqueous solution.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 16, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Jun Hatakeyama