Patents Examined by Christopher Young
  • Patent number: 9329488
    Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 9329471
    Abstract: Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 3, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guoxiang Ning, Xintuo Dai, Huang Liu, Chin Teong Lim
  • Patent number: 9331022
    Abstract: A pattern from a patterning device is applied to a substrate by a lithographic apparatus. The applied pattern includes product features and metrology targets. The metrology targets include large targets and small targets which are for measuring overlay. Some of the smaller targets are distributed at locations between the larger targets, while other small targets are placed at the same locations as a large target. By comparing values measured using a small target and large target at the same location, parameter values measured using all the small targets can be corrected for better accuracy. The large targets can be located primarily within scribe lanes while the small targets are distributed within product areas.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 3, 2016
    Assignee: ASML Netherlands B.V.
    Inventors: Maurits Van Der Schaar, Patrick Warnaar, Kaustuve Bhattacharyya, Hendrik Jan Hidde Smilde, Michael Kubis
  • Patent number: 9323141
    Abstract: Disclosed is a method for producing a substrate with a multilayer reflective film for EUV lithography including a multilayer reflective film disposed on a principal surface of a substrate, the method including a multilayer reflective film formation step of forming the multilayer reflective film on the principal surface of the substrate in such a manner that the multilayer reflective film has a slope region in which the film thickness is decreased in a direction from the inside to the outside of the substrate on a peripheral portion of the principal surface, and a fiducial mark formation step of forming fiducial marks in the slope region by removing at least a portion of the multilayer reflective film, the fiducial marks serving as references for a defective location indicated by defect information with respect to the surface of the substrate with the multilayer reflective film.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: April 26, 2016
    Assignee: HOYA CORPORATION
    Inventors: Tsutomu Shoki, Kazuhiro Hamamoto
  • Patent number: 9323142
    Abstract: Methods of reducing registration errors of photomasks and photomasks formed using the methods are provided. The method may include forming a plurality of photomask patterns on a substrate and determining registration errors of the plurality of photomask patterns. The method may further include forming a plurality of stress-producing portions in the substrate to reduce the registration errors by considering exposure latitude variations.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Choi, Sukjong Bae, Inkyun Shin, Jeonghyeon Lee
  • Patent number: 9323140
    Abstract: A method and system for fracturing or mask data preparation is disclosed in which a plurality of charged particle beam shots is determined which will produce a pattern on a reticle, where the reticle is to be used to form an aerial image on a resist-coated substrate using an optical lithographic process. A simulated reticle pattern is then calculated from the plurality of charged particle beam shots. A calculated aerial substrate image is then calculated using the simulated reticle pattern, and a shot in the plurality of shots is modified to improve the calculated aerial substrate image. Similar methods for forming a pattern on a reticle and for manufacturing an integrated circuit are also disclosed.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: April 26, 2016
    Assignee: D2S, Inc.
    Inventor: Akira Fujimura
  • Patent number: 9312101
    Abstract: A method includes scanning a lithography mask with a repair process, and measuring back-scattered electron signals of back-scattered electrons generated from the scanning. An endpoint is determined from the back-scattered electron signals. A stop point is calculated from the endpoint. The step of scanning is stopped when the calculated stop point is reached.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Lin Chen, Chih-Wei Wen, Chung-Hung Lin
  • Patent number: 9305799
    Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen
  • Patent number: 9291916
    Abstract: A substrate is loaded onto a substrate support of a lithographic apparatus, after which the apparatus measures locations of substrate alignment marks. These measurements define first correction information allowing the apparatus to apply a pattern at one or more desired locations on the substrate. Additional second correction information is used to enhance accuracy of pattern positioning, in particular to correct higher order distortions of a nominal alignment grid. The second correction information may be based on measurements of locations of alignment marks made when applying a previous pattern to the same substrate. The second correction information may alternatively or in addition be based on measurements made on similar substrates that have been patterned prior to the current substrate.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: March 22, 2016
    Assignee: ASML Netherlands B.V.
    Inventors: Stefan Cornelis Theodorus Van Der Sanden, Richard Johannes Franciscus Van Haren, Hubertus Johannes Gertrudus Simons, Remi Daniel Marie Edart, Xiuhong Wei, Irina Lyulina, Michael Kubis
  • Patent number: 9287125
    Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ya Hui Chang, Ru-Gun Liu, Tsong-Hua Ou, Ken-Hsien Hsieh, Burn Jeng Lin
  • Patent number: 9285682
    Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
  • Patent number: 9285673
    Abstract: A photomask having a partial-thickness assist feature and a technique for manufacturing the photomask are disclosed. In an exemplary embodiment, the photomask includes a mask substrate, a reflective structure disposed on the mask substrate, and an absorptive layer formed on the reflective structure. A printing feature region and an assist feature region are defined on the mask. The absorptive layer has a first thickness in the printing feature region and a second thickness in the assist feature region that is different from the first thickness. In some such embodiments, the second thickness is configured such that radiation reflected by the assist feature region does not exceed an exposure threshold of a photoresist of a target.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Min Huang, Chia-Jen Chen, Hsin-Chang Lee, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9274412
    Abstract: A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle pattern. A substrate image is calculated, based on using the simulated reticle pattern in an optical lithographic process to form the substrate image. A system for OPC is also disclosed.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: March 1, 2016
    Assignee: D2S, Inc.
    Inventor: Akira Fujimura
  • Patent number: 9268207
    Abstract: A method of manufacturing a reflective mask blank for EUV lithography with a resist film, includes preparing a reflective mask blank provided with three or more concave or convex fiducial marks each formed by at least two lines placed to extend along any one of virtual lines that cross at an intersection point, at least one of the lines of the fiducial mark being placed to extend along each of the virtual lines; forming a resist film on the reflective mask blank; detecting fiducial positions corresponding to the intersection points of the fiducial marks by scanning with an electron beam or an ultraviolet light; and exposing specific areas of the resist film including circular areas centered at the fiducial positions of the respective fiducial marks with a radius of 1.5W, where W is the maximum value of a width of the line of the respective fiducial marks.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: February 23, 2016
    Assignee: Asahi Glass Company, Limited
    Inventor: Yoshiaki Ikuta
  • Patent number: 9268211
    Abstract: The invention relates to a lithographic apparatus including an illumination system configured to condition a radiation beam, a patterning device support constructed to support a patterning device, the patterning device being capable of imparting the radiation beam with a pattern in its cross-section to form a patterned radiation beam, a substrate support constructed to hold a substrate; a projection system configured to project the patterned radiation beam onto a target portion of the substrate, and an encoder-type measurement system configured to at least during projection of the patterned radiation beam onto a target portion of the substrate continuously determine a position quantity of a patterning device supported on the patterning device support using a grid or grating provided on the patterning device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 23, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Jan Van Eijk, Engelbertus Antonius Fransiscus Van Der Pasch, Johannes Petrus Martinus Bernardus Vermeulen
  • Patent number: 9268214
    Abstract: A method for fracturing or mask data preparation is disclosed, in which a set of shots is determined, where each shot will direct a circular or nearly-circular dosage pattern to a surface, where each shot comprises a shot dosage, and in which the set of shots is output. A method for forming patterns on a surface using charged particle beam lithography is also disclosed, in which a stencil is provided comprising one or more circular apertures, and where a plurality of circular patterns of different sizes are formed on the surface using a single aperture, by varying the shot dosage.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: February 23, 2016
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Michael Tucker
  • Patent number: 9268209
    Abstract: A method of forming a pattern is disclosed. At first, a layout pattern is provided to a computer system. The layout pattern includes at least a first strip pattern and at least a second strip pattern, and a width of the second strip pattern is substantially larger than a width of the first strip pattern. Subsequently, the second strip pattern neighboring the first strip pattern is defined as a selected pattern. Then, an assist pattern is formed in the selected pattern, and the assist pattern does not overlap a center line of the selected pattern. The layout pattern and the assist pattern are further outputted through the computer system onto a mask.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: February 23, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Shiang Yang
  • Patent number: 9261774
    Abstract: The present disclosure provides one embodiment of an extreme ultraviolet (EUV) mask. The EUV mask includes a first state and a second state different from each other; a first main polygon and a second main polygon adjacent to the first main polygon; a plurality of sub-resolution assist polygons; and a field. Each of the first and second main polygons, the sub-resolution assist polygons, and the field has an associated state. The state assigned to the first main polygon is different from the state assigned to the second main polygon. The plurality of assist polygons are assigned a same state, which is different from a state assigned to the field.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9256123
    Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9239516
    Abstract: A reflective extreme ultraviolet mask includes a mask substrate having an exposing region and a peripheral region, the mask substrate including a light-scattering portion in the peripheral region, a reflective layer on an upper surface of the mask substrate, the reflective layer having a first opening exposing the light-scattering portion, and an absorbing layer pattern on the reflective layer, the absorbing layer pattern having a second opening in light communication with the first opening.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: January 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Geun Kim, Dong-Wan Kim, Dong-Gun Lee, Seong-Sue Kim