Patents Examined by Christy L. Novacek
  • Patent number: 7498269
    Abstract: Silicon electrode assembly decontamination cleaning methods and solutions, which control or eliminate possible chemical attacks of electrode assembly bonding materials, comprise ammonium fluoride, hydrogen peroxide, acetic acid, optionally ammonium acetate, and deionized water.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 3, 2009
    Assignee: Lam Research Corporation
    Inventors: Daxing Ren, Hong Shih
  • Patent number: 7498261
    Abstract: A metal film-forming method of the present invention can form a metal film having different film qualities in the thickness direction, in a continuous manner using a single processing solution. The metal film-forming method including: providing a substrate having embedded interconnects formed in interconnect recesses provided in a surface of the substrate; and forming a metal film, having different film qualities in the thickness direction, on surfaces of the interconnects in a continuous manner by changing the flow state of a processing solution relative to the surface of the substrate while keeping the surface of the substrate in contact with the processing solution.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: March 3, 2009
    Assignee: Ebara Corporation
    Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga, Akira Owatari
  • Patent number: 7491647
    Abstract: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: February 17, 2009
    Assignee: Lam Research Corporation
    Inventors: S. M. Reza Sadjadi, Peter Cirigliano, Ji Soo Kim, Zhisong Huang, Eric A. Hudson
  • Patent number: 7482690
    Abstract: A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers is deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: January 27, 2009
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang
  • Patent number: 7476554
    Abstract: A substrate processing method of the present invention includes the steps of placing a substrate inside a vacuum container containing particles and processing the substrate inside the container while moving the substrate at a predetermined relative velocity of the substrate to the container. In this case, an allowable upper limit of the number or density of defects produced at the substrate due to the particles in the process for the substrate is determined, and the predetermined relative velocity is set at a value equal to or smaller than the relative velocity obtained when the number or density of defects reaches the upper limit.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: January 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Toshio Kaneko, Toru Nishiwaki
  • Patent number: 7473590
    Abstract: According to an embodiment of the invention, a lower transistor is formed on a semiconductor substrate, and an upper thin film transistor is formed on the lower transistor. A body contact plug is formed to penetrate an upper gate electrode of the upper thin film transistor and a body pattern, and to electrically connect with a lower gate electrode of the lower transistor. The body contact plug uses a contact hole to apply an electrical signal to the upper gate electrode of the upper thin film transistor, so additional volume is not necessary. Since the upper gate electrode is electrically connected to the body pattern through the body contact plug, the floating body effect of the upper thin film transistor can be improved. Therefore, a semiconductor device is provided with the high performance required to realize a highly-integrated semiconductor device.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: January 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Hoon Lim, Hoo-Sung Cho
  • Patent number: 7468325
    Abstract: A method of cleaning a silicon nitride layer on a substrate is provided to effectively remove negative-charged impurities such as polymer and particle from the silicon nitride layer. In the method, the zeta potential of the silicon nitride layer is changed from positive to negative, and then the silicon nitride layer is cleaned with a first solution selected from an alkali solution and an NC-2 solution. So the negatively-charged impurities can be easily removed due to a repulsion force. The substrate can be treated with spin scrubber or quick dump rinse before and/or after the changing of the zeta potential. To change the zeta potential, the substrate can be dipped into a second solution such as an SC-1 solution, an NC-2 solution, and an alkali solution.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: December 23, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Dae Heok Kwon
  • Patent number: 7459394
    Abstract: Methods of manufacturing semiconductors are disclosed. One example method includes forming a trench through a dual damascene process, depositing a barrier metal layer on the overall surface, and depositing copper in the trench to form a copper line. The example method may also include performing a wet etching process to remove the top portion of the copper line, depositing a barrier layer on the etched copper line, and performing a planarization process to flatten the barrier layer.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: December 2, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ki Min Lee
  • Patent number: 7452751
    Abstract: Semiconductor device includes a pair of substrates (1, 2) disposed oppositely, semiconductor elements (5, 6) formed in the substrates (1, 2), respectively, and having semiconductor circuits (3, 4) and electrodes (7, 8), respectively, a wiring conductor (9) interposed between the electrodes (7, 8), and a through electrode (12) extending through one substrate (1) and connected to the electrode (7) via the wiring conductor (9). The other substrate (2) is disposed laterally of the through electrode (12). Surface of the through electrode (12) projecting from the one substrate (1) and lateral surface of the element (6) are coated with an insulation material (13). The through electrode (12) has one end exposed in a back surface of the one substrate (1), while other end is positioned flush with a back surface of the other substrate (2), being exposed.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: November 18, 2008
    Assignees: Renesas Technology Corp., Kabushiki Kaisha Toshiba, Rohm Co., Ltd.
    Inventors: Yoshihiko Nemoto, Kazumasa Tanida, Kenji Takahashi
  • Patent number: 7446028
    Abstract: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g.,metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: November 4, 2008
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Warren M. Farnworth
  • Patent number: 7442636
    Abstract: A method for the pre-treatment of a wafer substrates with exposed metal surfaces is disclosed. The pre-treatment reduces oxidation of the exposed metal surfaces during subsequent supercritical cleaning processes.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: October 28, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Joseph Hillman
  • Patent number: 7422962
    Abstract: A method of singulating electronic devices, including aligning a saw blade over a lid street disposed on a lid substrate that is disposed over a device substrate. An electronic device that includes a bond pad is disposed on the device substrate, wherein the lid street is disposed over the bond pad. In addition, the method also includes sawing partially through the lid street to form a trench in the lid street. The trench includes a trench bottom in the lid substrate.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: September 9, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Zhizhang Chen, Steven R Geissler
  • Patent number: 7422922
    Abstract: In a photoelectric conversion device using a semiconductor electrode composed of semiconductor nanoparticles, the semiconductor electrode is made by coating and drying a paste containing a binder and semiconductor nanoparticles dispersed therein on a transparent conductive substrate, and pressing the paste to bond the semiconductor nanoparticles onto the transparent conductive substrate while heating it to a temperature in the range from 30° C. to the softening temperature of the transparent conductive substrate, or, if the semiconductor nanoparticles retain a sensitizing dye, to a temperature in the range from 30° C. to lower one of the softening temperature of the transparent conductive substrate and the deactivation temperature of the sensitizing dye.
    Type: Grant
    Filed: December 25, 2003
    Date of Patent: September 9, 2008
    Assignee: Sony Corporation
    Inventors: Masahiro Morooka, Yusuke Suzuki, Kazuhiro Noda
  • Patent number: 7419915
    Abstract: A method using an etchant and a laser for localized precise heating enables precise etching and release of MEMS devices with improved process control while expanding the number of materials used to make MEMS, including silicon-dioxide patterned films buried in and subsequently released from bulk silicon, as a direct write method of release of patterned structures that enables removal of only that material needed to allow the device to perform to be precisely released, after which, the bulk material can be further processed for additional electrical or packaging functions.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: September 2, 2008
    Assignee: The Aerospace Corporation
    Inventors: Margaret H. Abraham, Henry Helvajian, Siegfried W. Janson
  • Patent number: 7419917
    Abstract: A method is used for producing nanoscale and microscale devices in a variety of materials, such as silicon dioxide patterned buried films. The method is inexpensive and reliable for making small scale mechanical, optical, or electrical devices and relies upon the implantation of ions into a substrate and subsequent annealing to form a stoichiometric film with the device geometry is defined by the implant energy and dose and so is not limited by the usual process parameters.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: September 2, 2008
    Assignee: The Aerospace Corporation
    Inventor: Margaret H. Abraham
  • Patent number: 7417297
    Abstract: SOI wafers are manufactured to have very thin device layers of high surface quality. The layer is ?20 nm in thickness, has an HF density of ?0.1/cm2, and a surface roughness of 0.2 nm RMS.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: August 26, 2008
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Reinhold Wahlich, Rüdiger Schmolke, Wilfried Von Ammon, James Moreland
  • Patent number: 7416969
    Abstract: A process for the production of a void-free semiconductor wafer for the electronics industry, comprising the steps of: applying a coating of a solder paste to a semiconductor wafer through a photoresist film; heating and applying a vacuum to the wafer in a reflow furnace with a controlled formic acid vapor ambient to for a first reflow to remove the flux and form void free solder bumps on the wafer; processing the wafer to remove the photoresist film; heating the wafer in a reflow furnace with a controlled formic acid vapor ambient for a second reflow to remove surface oxides from the wafer and to form the solder into final void free metal solder bumps.
    Type: Grant
    Filed: February 26, 2005
    Date of Patent: August 26, 2008
    Inventor: Jian Zhang
  • Patent number: 7416967
    Abstract: According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: August 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Tsuchiya, Masato Koyama, Masahiko Yoshiki
  • Patent number: 7410903
    Abstract: The invention includes a template comprising one or both of CdS and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can include two or more separated segments. The template can be utilized for patterning a plurality of substrates. For instance, the substrates can be provided to have masking layers thereover, and the CdS and/or CdSe can be utilized as catalytic material to sequentially impart patterns in the masking layers. The imparting of the patterns can modify some regions of the masking layers relative to others, and either the modified or unmodified regions can be selectively removed to form patterned masks from the masking layers. Patterns from the patterned masks can then be transferred into the substrates.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Krupakar M. Subramanian
  • Patent number: 7407889
    Abstract: The present invention improves a method of forming a surface unevenness using a difference in etching rates, and relaxes limitations on substrates in this method. In a method of the present invention, an uneven surface is formed by a method including applying pressure to a predetermined region in a surface of a thin film formed on a substrate, and etching a region including at least a portion of the predetermined region and at least a portion of the reminder of the surface that excludes the predetermined region. An etching rate difference within the thin film increases freedom in selecting a substrate material.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: August 5, 2008
    Assignees: Nippon Sheet Glass Company, Limited, Olympus Corporation
    Inventors: Keiji Tsunetomo, Shinya Okamoto, Yasuhiro Saito, Junji Kurachi, Akihiro Koyama, Hirotaka Koyo, Takeshi Hidaka, Hiroaki Kasai, Masamichi Hijino, Yasushi Nakamura