Abstract: A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.

Abstract: A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).

Abstract: A variable sample rate recursive digital filter is an adaptive digital filter where its coefficients are recalculated for each sample rate being processed in such a way as to maintain a constant frequency rate for all sample rates. An equivalent resampling is done by taking the ratio of the bilinear transforms at the respective sample rates. From an initial or calibrated sample rate and a corresponding initial filter coefficient, a new filter coefficient for a new sample rate is obtained by multiplying the initial filter coefficient by a constant or coefficient factor that is a function of the initial filter coefficient and a ratio of the initial and new sample rates: zFactor(z,R):=(1/z){(z(1+R)+(1?R))/(z(1?R)+(1+R))} The resulting new filter coefficient provides the adaptive digital filter with a constant frequency response when compared to the initial sample rate frequency response.

Abstract: The present invention relates to a method and system for providing a single accumulatable packed multi-way addition instruction having the functionality of multiple instructions without causing any timing problems in the execute stage. Specifically, the accumulatable packed multi-way combination instruction may be associated with at least one destination and a plurality of operands and set a polarity of each of a plurality of source operands derived from the plurality of operands, if requested by the instruction. The instruction also may add selected pairs of the plurality of source operands in predetermined orders to obtain at least one result and, if requested by the instruction, accumulating the plurality of results to obtain at least one accumulated result; output at least one predetermined pair of the at least one result and the at least one accumulated result; and accumulate condition codes for each of the at least one result and the at least one accumulated result, if requested by the instruction.

Abstract: A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear.

Abstract: A method for finding optimal filter coefficients for a filter given an input data sequence and an objective function is disclosed. The method includes selecting a wavelet basis having k parameters and minimizes the k parameters according to the predetermined objective function. The wavelet basis is reparameterized into k/2 rotation parameters and factorized into a product of rotation and delay matrices. The k/2 rotation parameters are provided for the rotation matrices and a data transform matrix is computed based on the product of the rotation and delay matrices. The input data sequence is converted into transformed data by applying the data transform matrix to the input data. The Jacobian of the data transform matrix and the input data sequence is determined and multiplied by the gradient vector with respect to the transformed data of the objective function.

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recorded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract: A filter (50) with interconnected modular basic units (10) and with a delay line (51), equipped with takeoff points, to furnish delayed sampling values (x1, . . . , xN; xi) of a digital signal (x). Each basic unit (10) contains a programmable weighting device (11, 12), a linkage device (13, 14), and a delay device (15), which delays the data conducted to it by a single period (T) of the sampling clock pulse or by a simple integer multiple thereof. The filter (50) further contains a programmable control device (52), which switches over or switches off a part of the data inputs (16, 17) of the basic unit (10) to achieve forward and/or backward filtering and/or sign inversion and/or a change of the active filter length.

Abstract: A method and processor for multiplication operation instruction processing are provided. Multiplication operation instructions are executed on source operands in data memory locations. The multiplication operation instructions are provided to perform complex multiplication operations. The multiplication operation instructions may generate the square of a multiplication source operand and generate the difference of a subtrahend source operand and a minuend source operand simultaneously. The square is output to a target accumulator specified in the multiplication operation instruction. The difference is output to a difference register specified in the multiplication operation instruction. In the alternative, the multiplication operation instructions may generate the sum of the square of multiplication source operand and an addition operand as well as generate the difference of a subtrahend source operand and a minuend source operand simultaneously.

Abstract: One embodiment of the present invention provides a system that receives a representation of the function ƒ and stores the representation in a memory. Next, the system performs an interval global optimization process to compute guaranteed bounds on a globally minimum value of the function ƒ(x) over a subbox X. This interval global optimization process applies term consistency to a set of relations associated with the function ƒ over the subbox X, and excludes any portion of the subbox X that violates any member of the set of relations. It also applies box consistency to the set of relations associated with the function ƒ over the subbox X, and excludes any portion of the subbox X that violates the set of relations.

Abstract: The present invention discloses a computer system and program product. A computer system including an algorithm for computing a characteristic value of a matrix comprising steps of; providing a first matrix comprising M rows and N columns (M-by-N matrix); providing second matrixes by randomly selecting rows from the first matrix, each of the second matrixes including predetermined numbers of rows smaller than the numbers of rows of the first matrix; computing the characteristic values for the second matrixes; plotting each of the characteristic values with respect to the predetermined numbers of rows; and extrapolating the plots to said number of rows of the first matrix so as to obtain a characteristic value of the first matrix.

Abstract: One embodiment of the present invention provides a system for finding the roots of a system of nonlinear equations within an interval vector X=(X1, . . . , Xn), wherein the system of non-linear equations is specified by a vector function ƒ=(ƒ1, . . . , ƒn). The system operates by receiving a representation of the interval vector X (which is also called a box), wherein for each dimension, i, the representation of Xi includes a first floating-point number, ?i, representing the left endpoint of Xi, and a second floating-point number, bi, representing the right endpoint of Xi. Next, the system performs an interval Newton step on X to produce a resulting interval vector, X?, wherein the point of expansion of the interval Newton step is a point, x, within the interval X, and wherein performing the interval Newton step involves evaluating ƒ(x) to produce an interval result ƒ1(x).

Abstract: The present invention relates to an interpolation method and an interpolation apparatus for a digital audio signal or a digital image signal that has a predetermined sampling cycle and quantization bit length, and in particular, to an interpolation method and an interpolation apparatus that can effectively reduce quantization noise in a digital signal that is obtained by information compression. In the method and apparatus according to the present invention, it is made to perform interpolation processing of signal levels in a interpolation object interval in a given digital signal in accordance with a predetermined function curve, which monotonously changes, with the interpolation object interval including a discontinuous part that exists between one signal interval, where the same gradation levels continue, and another signal interval, which is adjacent to the one signal interval and in which the same gradation levels that are different continue.

Abstract: One embodiment of the present invention provides a computer-based system for solving a system of nonlinear equations specified by a vector function, f, wherein f(x)=0 represents ƒ1(x)=0, ƒ2(x)=0, ƒ3(x)=0 . . . , ƒn(x)=0, wherein x is a vector (x1, X2, X3, . . . xn). The system operates by receiving a representation of a subbox X=(X1, X2, . . . , Xn), wherein for each dimension, i, the representation of Xi, includes a first floating-point number, ai, representing the left endpoint of Xi, and a second floating-point number, bi, representing the right endpoint of Xi. The system stores the representation in a computer memory. Next, the system applies term consistency to the set of nonlinear equations, ƒ1(x)=0, ƒ2(x)=0, ƒ3(x)=0, . . . , ƒn,(x)=0, over X, and excludes portions of X that violate the set of nonlinear equations. The system also applies box consistency to the set of nonlinear equations over X, and excludes portions of X that violate the set of nonlinear equations.

Abstract: One embodiment of the present invention provides a system for finding zeros of a function, ƒ, within an interval, X, using the interval version of Newton's method. The system operates by receiving a representation of the interval X. This representation including a first floating-point number, a, representing the left endpoint of X, and a second floating-point number, b, representing the right endpoint of X. Next, the system performs an interval Newton step on X, wherein the point of expansion is the midpoint, x, of the interval X. Note that performing the interval Newton step involves evaluating ƒ(x) to produce an interval result ƒI(x). If ƒI(x) contains zero, the system evaluates ƒ(a) to produce an interval result ƒI(a). It also evaluates ƒ(b) to produce an interval result ƒI(b).

Abstract: An averaging measurement circuit comprises a register successively storing a series of data words having a plurality of bits and providing, for each of said data words, a first output consisting of all of the plurality of bits of the data word and a second output consisting of a number of the higher order bits of the data word. A subtracter subtracts each second output of the register from a corresponding data sample and outputs the corresponding subtraction result. An adder adds each first output of the register to a corresponding subtraction result and storing the result in the register.

Abstract: An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number to an integer part and a fractional part and outputs the integer part and the fractional part. The fractional part is an N-bit number and divided into K parts which have N1, N2, . . . , NK bits respectively, wherein N=N1+N2+ . . . +NK. Each of the exponential tables receives one of the K parts divided from the fractional part and outputs a result. The multiplier receives all results from the exponential tables and outputs a mantissa. The integer part outputted form the transforming device is an exponent.

Abstract: A square root extractor includes only multipliers, summers, delay elements, and a scaler so that the square root of a signal may be produced without complex computations.

Abstract: A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be compared. The first circuit is configured to generate a vector indicative of whether or not bits in the first operand and the second operand are equal. The second circuit receives the vector, and generates an indication of the first bit, beginning with the most significant bit, at which the first operand and the second operand differ. The third circuit receives the indication, and generates an indication of whether or not the first operand is greater than the second operand. In one embodiment, the first, second, and third circuits are included in a combined magnitude compare/count leading zero circuit.

Abstract: A method and apparatus are used to generate FFT data addresses based upon a computation stage value and a computation step value within that computation stage. The method includes the steps of generating a first data address by insertion at a bit insertion position a first bit between existing bits of a binary word and generating a second data address by inserting at the bit insertion position a second bit between existing bits of the binary word, wherein the binary word represents the computation step value. The apparatus includes a series of consecutive bit cells that generate the desired data addresses based upon a decoded value of the computation stage.