Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract: Over-sampled timing signal jitter tolerance is improved in a q-times over-sampled architecture by phase-sampling the timing signal to produce a plurality of input phase samples &phgr;in, where &phgr;in&egr;{&phgr;1, &phgr;2, . . . , &phgr;q}. An output phase value &phgr;out=&phgr;in is initialized for each input sample &phgr;in. A difference vector di is derived for each input sample &phgr;in, where di=Fj(n,k). F denotes a vector operation, n is the number of input samples, k is a pre-defined threshold value, and j represents a filter order value. A predefined scaling coefficient ai is applied to each difference vector di to produce a corresponding set of scaled difference vectors ai di. The scaled difference vectors are summed: d j = ∑ i = 1 n ⁢ a i ⁢ d i .

Abstract: A fractional sequence generator for use in a F-N synthesizer includes a multi-accumulator structure providing a plurality of carry-out signals for application to an adder through a recombination network to generate an output fractional sequence, S, having an average value given by avg(S)=C/D, where C/D is the desired fractional part of the divisor, and denominator, D, is programmable. Illustratively, contents of a n-bit accumulator in each accumulator is augmented by a function of the programmable denominator value upon a carry-out of the associated n-bit adder in that accumulator.

Abstract: A method for calculating the power of an integer raised to a constant real number. The method may be used to process digital signals, which are encoded in such a fashion as to require such processing. An embodiment of the present invention first receives a segment of a bitstream. Next, the process determines whether an integer value of the segment is within a look-up table. The look-up table contains a list of integers and a corresponding list of the integers raised to the power of a real number. If the integer value is within the look-up table, the process indexes the look-up table with the integer value to determine substantially the value of the integer raised to the real power. If, however, the integer value is not within the look-up table, the process indexes the table with a plurality of integers which are within the table to approximate the value of the segment from the bitstream raised to the real power. The process repeats these steps for each segment in the signal bitstream.

Abstract: A method of determining a biased leading-zero count for a floating-point operation is disclosed. First, a binary vector is divided into subvectors. Then, multiple subvector leading-zero counts are generated. The subvector leading-zero counts are biased by a constant amount. Next, one or more prefix bits are calculated. Finally, at least a portion of a selected subvector leading-zero count is concatenated to the prefix bits to yield a total leading-zero count for the binary vector.

Abstract: An enhanced architecture time-shared data correlator for performing a predetermined number of correlation processes. A data shift register receives input data and loads the input data. A reference shift register receives reference data and loads and circulates the reference data. A pulse correlator connected to the shift register and the reference shift register correlates the input data with the corresponding reference data and provides a pulse correlator output. An accumulator connected to the pulse correlator receives and adds the pulse correlator outputs from the correlation processes to produce a correlator output corresponding to the predetermined number of correlation processes.

Abstract: A multimedia processor is capable of concurrently carrying out processing tasks at different degrees of precision suitable for a variety of purposes and displays high performance of consecutively outputting a new cumulative result by adding or subtracting a result of multiplication to or from an existing cumulative result. To prevent the processing precision from deteriorating in applications where the processing precision is critical, critical processing precision is assured by multiplication of a signed number by an unsigned number. A partial product output by a multiplication and an existing cumulative result are supplied. The number of inputs is counted by a carry-save counter based on a 7-3 counter. A ripple adder is employed on the low-order-digit side where propagation of carry is completed early. On the other hand, a carry select/look-ahead adder is employed on the high-order-digit side to speed up the propagation of a carry.

Abstract: One embodiment of the present invention provides an apparatus for facilitating an addition operation between two N-bit numbers, wherein the apparatus has a regular structure. The apparatus includes a carry circuit for generating at least one carry signal for the addition operation, wherein the carry circuit includes a plurality of logic blocks organized into rows that form approximately logN successive stages of logic blocks. Each of these logic blocks provides current for at most a constant number of inputs in a successive stage of logic blocks. Additionally, within a given stage of logic blocks, outputs from multiple logic blocks are ganged together to drive a signal line that feeds multiple inputs in a successive stage of logic blocks. Furthermore, there are at most a constant number of lateral tracks in a planar layout of signal lines between the successive stages of logic blocks.

Abstract: Embodiments of a pyramid filter are described.

Abstract: A method for filtering signals from a nonlinear dynamical system is provided. An initial enhanced point is set to a noisy point obtained from the signals. An intermediate enhanced point is estimated. A new enhanced point is calculated using the estimated point and a weighting constant. Estimation of an intermediate enhanced point and calculation of a new enhanced point are iterated until the computed point converges to a true enhanced point which represents a noise reduced signal to provide filtered signals, wherein the new enhanced point is computed by the equation {circumflex over (x)}n(i)={circumflex over (x)}n(i−1)+K3[{circumflex over (x)}n(i,temp)−{circumflex over (x)}n(i−1)] wherein {circumflex over (x)}n(i) is the new enhanced point, {circumflex over (x)}n(i-temp) is the intermediate enhanced point for iteration i, {circumflex over (x)}n(i−1) is the enhanced point at iteration i−1, and K3 is a weighing constant.

Abstract: A Galois field multiplier system includes a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; and a storage circuit for supplying to the Galois field linear transformer circuit a set of coefficients for predicting the modulo remainder for predetermined irreducible polynomial.

Abstract: Fast transforms that use multiple scaled terms is disclosed. The discrete transforms are split into sub-transforms that are independently calculated using multiple scaling terms on the transform constants. The effect of the scaling for the transform coefficients may optionally be handled by appropriately scaling the quantization values or any comparison values. Further, optimal representations of the scaled terms for binary arithmetic are found. The resulting calculations result in fast transform calculations, decreased software execution times and reduced hardware requirements for many linear transforms used in signal and image processing application, e.g., the DCT, DFT and DWT.

Abstract: A method for converting between source coordinates in a source coordinate system and target coordinates in a target coordinate system includes the step of defining a coordinate system conversion tree extending from a root coordinate system and branching to a plurality of other coordinate-systems including the source and target coordinate systems so that the source and target coordinate systems are connected to a common coordinate system other than the root coordinate system. Coordinate conversions are performed between the source and target coordinates along branches extending from the source coordinate system to the common coordinate system and to the target coordinate system without returning to the root coordinate system. Contextual data is associated with the coordinates to permit conversion to an adjacent coordinate system.

Abstract: A method and apparatus for signal and noise processing employs a D Scale, which assigns the results of arithmetic operations to a set of values of controlled density and value. The signal processor has two components, a set of mappings from pairs of points in a D Scale into a point in a D Scale, and a map of measured values, into D Scale points. A tight variance of the resolution is achieved by using prime sub-scales to fill in the D Scale. Fewer sample points attain the same mean resolution, with a tight variance, as a high uniform sampling rate. The invention bounds the round-off errors of sequential calculations, and decouples actual noise from the artifact created by calculation round-off errors. The invention provides a Discrete Fourier Transform (DFT) of a signal or image as an example of a continuous-to-discrete transformation.

Abstract: A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of the population count and bit shift circuits so that the execution of operations is more balanced, which, in effect, increases computational speed and efficiency. An apparatus that integrates population count circuitry and bit shift circuitry has also been developed. The apparatus comprises a plurality of dynamic stages followed by static stages. The dynamic stages involve the use of dynamic nodes which represent values dependent upon values of individual bits in the pointer and the sparse vector. The apparatus further allows for an expansion through circuit repetition so that the topology of the apparatus can change according to the size of the pointer and sparse vector.

Abstract: Interleaved type processing includes a preprocessing phase in which for each initial symbol received an auxiliary symbol that includes N auxiliary complex samples is formulated, and a processing phase that includes for each auxiliary symbol an inverse Fourier transform calculation of size N. The processing phase includes elementary processing of the butterfly type corresponding to several stages of a general butterfly-like calculation graph. The various stages of the graph are implemented within a pipelined architecture. Upon receiving an initial symbol, two separate random access memories are simultaneously used to respectively store in a first memory the auxiliary symbol corresponding to this initial symbol, and to perform on the basis of the content of the second memory the elementary processing corresponding to a first stage of the graph. The two memories are swapped with each new receipt of an initial symbol.

Abstract: An SRT division unit for performing a novel SRT division algorithm is presented. The novel SRT division algorithm comprises a method for performing SRT division using a radix r. As one skilled in the art will appreciate, the radix r dictates the number of quotient-bits k generated during a single iteration. The relationship between radix r and the number of quotient-bits k generated in a single iteration is r=2k. The number of iterations needed to determine all quotient-digits is N, such that N=54/k for a 64 bit floating point value. In accordance with one embodiment of the present invention, the SRT division unit generates a scaling factor M, which comprises scaling sub-factors M1 and M2 according to the relationship M=r*M1+M2. Next, the division unit generates a scaled divisor Y by multiplying a divisor DR by scaling factor M, such that said scaled divisor Y=DR*M=r(DR*M1)+DR*M2.

Abstract: An architecture for a multiply and accumulate two-dimensional separable symmetric filter. The architecture includes a binary tree adder producing sums of samples of an incoming signal. A multiplier then multiplies sums from the binary tree adder with filter coefficients producing filtered products. An accumulation adder to sums the filtered products and produce a filtered output.

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up.

Abstract: The present invention is an apparatus and a method for generation of random numbers. The apparatus comprises an alpha-radiation source, such as Am 241, for which the decay product produces no secondary radiation with the energy equal or higher than that of the prime alpha radiation. The alpha particles emitted by the isotope and having reached the detector have a narrow energy spectrum and, hence, produce identical electrical pulses in a detector. An alpha-particle detection system is provided which includes a differential discriminator in combination with a logical selector. This combination of elements allows a positive identification of individual events of alpha-decay in the alpha-radiation source to be made and filters out any other signals produced by different radiation sources both inside and outside the apparatus. An electronic unit processes the stream of identical electric pulses into a stream of random numbers.