Abstract: One embodiment of the present invention provides a system for performing a minimum/maximum computation for an interval operation. The system operates by receiving at least four floating-point numbers, including a first floating-point number, a second floating-point number, a third floating-point number and a fourth floating-point number. Next, the system computes a minimum/maximum of the at least four floating-point numbers, wherein if the at least four floating-point numbers include one or two default NaN (not-a-number) values and the remaining values are not default NaN values, the default NaN values are ignored in computing the minimum/maximum.

Abstract: A method and apparatus for a multi-purpose adder is described. The method includes calculation of an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal. Generation of an initial carryout signal for each calculated initial sum is then performed. Next, an intermediate sum for each group of M-initial sums according to a respective initial carryout value of each initial sum is then generated. Once generated, an intermediate carryout value for each generated intermediate sum is then calculated. Finally, a final sum is calculated from the intermediate sums generated according to a respective intermediate carryout of each intermediate sum.

Abstract: A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a combination of carry increment adder (CIA) and carry lookahead adder (CLA) circuit is used in the middle block.

Abstract: When numerically integrating an integrand function A over an unbounded domain, a vector map f converts an m (m≧1)-dimensional vector into an m-dimensional vector wherein a multidimensional density function &rgr; of the limiting distribution resulting from repeatedly applying the map f to a predetermined m-dimensional vector u is analytically solvable. A first storage unit stores an m-dimensional vector x, a second storage unit stores a scalar value w, a first computing unit computes a vector x′=f(x), a second computing unit computes a scalar value w′=A(x)/&rgr;(x), an update unit updates values in the first and second storage units and by storing the vector x′ on the first storage unit and adding the scalar value w′ to a value to be stored in the second storage unit, and an output unit computes a scalar value s=w/(c+1) when the number of update times by the update unit becomes c (c≧1) and outputs the result.

Abstract: A computer algebra system including algebraic expression transformations with a display of domain of definition constraints only when a domain of definition differs from that of an antecedent expression.

Abstract: One embodiment of the present invention provides a system for solving a nonlinear equation through interval arithmetic. During operation, the system receives a representation of the nonlinear equation ƒ(x)=0, as well as a representation of an initial interval, X, wherein this representation of X includes a first floating-point number, XL, for the left endpoint of X, and a second floating-point number, XU, for the right endpoint of X. Next, the system symbolically manipulates the nonlinear equation ƒ(x)=0 to solve for a first term, g1(x), thereby producing a modified equation g1(x)=h1(x), wherein the first term g1(x) can be analytically inverted to produce an inverse function g1−1(x). The system then plugs the initial interval X into the modified equation to produce the equation g1(X′)=h1(X), and solves for X′=g1−1[h1(X)].

Abstract: A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i−1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.

Abstract: A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module receives the sum output of a first of the plurality of full adders and a carry output of a second of the plurality of full adders and provides an exclusive-OR output. An AND logic module has a plurality of inputs and an AND output, wherein the exclusive-OR output is electrically connected to one of the plurality of inputs of the AND logic module, and the AND output provides a signal that indicates whether the first data equals the sum of the second data and third data.

Abstract: A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k digit data D (=Dm/k−1Dm/k−2 . . . Di . . . DiDo). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized.

Abstract: A method and device for use, e.g., in a mobile telephone, for self-clocked controlled pseudo random noise (PN) sequence generation comprises a plurality of sequence generator units for outputting a plurality of sequence values (Zt) on the basis of a plurality of clock values (Ct), and step pattern generators for selecting a step pattern, comprising said plurality of clock values (Ct), from a plurality of possible step patterns on the basis of a step pattern select signal (Wt). Thus, a flexible and efficient self-clocked controlled pseudo random noise (PN) sequence generation is obtained.

Abstract: Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply operations on a series of smaller operands to form partial products, and adding the partial products together. Data manipulation instructions are used to reposition 16-bit segments of the 32-bit operands into positions that allow the multi-media parallel multiply instructions to compute partial products, and the partial products are then added together to form the result. In every embodiment, the present invention achieves better latencies than the prior art method of performing integer multiply operations provided by the IA-64 architecture.

Abstract: A non-integer fractional divider is disclosed. According to the present invention, the non-integer fractional divider comprises means for dividing a reference clock signal having a period ‘P’ by a non-integer ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio ‘K’. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the non-integer part of the non-integer ratio.

Abstract: An averaging circuit includes: input signal nodes for providing input signals 330; a multiplexing circuit 320 coupled to the input signal nodes for switching between the input signals 330 to create a time waveform; a low pass filter 300 coupled to an output 340 of the multiplexing circuit 320 for filtering the time waveform to create an average signal; and an average replication circuit 310 coupled to an output 350 of the low pass filter 300.

Abstract: A method and corresponding apparatus for determining the centroid (Vc) of a waveform signal being sampled at a set of parameter values (Vi, i=1, . . . , n) yielding a corresponding set of sampled amplitudes (Ai, i=1, . . . , n), each parameter value and corresponding amplitude forming a sampled point (Vi, Ai), the method including the steps of: selecting an amplitude at which to create an interpolated point; interpolating a first parameter value corresponding to the amplitude selected in the step of selecting an amplitude; and performing a centroid calculation using only the sampled points with an amplitude greater than a predetermined threshold. The waveform is sometimes sampled in the presence of background noise, and the method sometimes also includes: estimating the background (Bi) for each value in the set of parameter values at which sampling is performed; and reducing the amplitude (Ai) of each sampled amplitude by the background (Bi) so estimated.

Abstract: A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an exponent portion of a standard length from a source without the FPU and transforms the denormal number into a normalized number having an exponent portion of an expanded length greater than the standard length, (2) a floating point execution core, coupled to the load unit, that processes the normalized number at least once to yield a processed normalized number, the expanded length of the exponent portion allowing the processed normalized number to remain normal during processing thereof and (3) a store unit, coupled to the floating point execution core, that receives the processed normalized number and transforms the processed normalized number back into a denormal number having an exponent portion of the standard length.

Abstract: A circuit for reducing the number of bits in a K bit value from K to N bits. The circuit generally comprises a first summing circuit, a control circuit, an error feedback circuit, a second summing circuit, and a processor. The first summing circuit may add an error offset value and the N+m MSB's of the K bit value to produce a result data value. The control circuit may generate a dither offset value. The error feedback circuit may receive m LSBs of the result data value and generate an error value in dependence on the m LSBs. The second summing circuit may add the dither offset value and the error value to provide the error offset value. The processor may selectively control generation of the dither offset value and the error value.

Abstract: A computer programmed to process a method for generating a sequence of random numbers of a 1/f noise has the following steps: 1). Determining a constant step &dgr; or instants of consideration t0 to tn; 2). Determining a desired spectral value &bgr;; 3). Determining the number n of the random numbers, to be generated, of a 1/f noise; 4). Determining an intensity constant const; 5). forming a covariance matrix C of dimension (n×n); and 6). Forming the Cholesky decomposition L of the covariance matrix C, with the following steps being carried out for each sequence, to be generated, of random numbers of a 1/f noise: 1). Forming a vector x of length n from random numbers normally distributed in [0,1], and 2). Generating a vector y of length n of the desired 1/f-distributed random numbers by multiplying the Cholesky-decomposition L by the vector x.

Abstract: An object of the present invention is to provide a multiply-accumulate unit with a rounding function which is capable of effecting 16-bit multiply-accumulate operations taking into account the position of an addend in a register. The multiply-accumulate unit with the rounding function has a selection inputting and expanding means 42 for expanding an addend from 31st-16th bits of 40-bit register 1 into 40-bit data and transmitting the 40-bit data to MAC (multiply-accumulate) unit 41 if control signal Position from an external source is “1”, and expanding an addend from 15th-0th bits of 40-bit register 1 into 40-bit data and transmitting the 40-bit data to MAC unit 41 if control signal Position is “0”. MAC unit 41 performs a multiply-accumulate operation on the 40-bit data, 16-bit data multiplicand B, and multiplier C.

Abstract: Apparatus and methods are provided for an improved on-the-fly rounding technique for digit-recurrence algorithms, such as division and square root calculations. According to one embodiment, only two forms of an intermediate result of an operation to be performed by a digit-recurrence algorithm are maintained. A first form is maintained in a first register and a second form is maintained in a second register. Responsive to receiving digits 1 to L−2 of the intermediate result from a digit recurrence unit, where L represents a number of digits that satisfies a predetermined precision for the operation, both forms of the intermediate result are updated by register swapping or concatenation under the control of load and shift control logic and on-the-fly conversion logic. Then, a rounded result is generated by determining digits dL−1 and dL and appending a rounded last digit to the appropriate form of the intermediate result.

Abstract: A longest common subprefix of two binary words p1 and p2 is identified based on bit strings ip1 and ip2 which are extensions of p1 and p2, and binary words n1 and n2 that define the length of p1 and p2. The bit strings and words are processed to set a “greater” output if p1>p2 and to set an “equal” output if p1=p2. A mask having a consecutive string of most significant bits having a first logical value is constructed to identify the matching subprefixes of p1 and p2.