Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.

Abstract: Switch circuitry is disclosed having a series stack of transistors coupled between first and second port terminals. A string of gate resistors having a common gate terminal is coupled to gates of the series stack of transistors. A bias control transistor has a bias control terminal and first and second current terminals. The second control terminal is coupled to a switch control terminal configured to receive on-state and off-state control voltages that transition the series stack of transistors between passing a radio frequency signal and blocking the radio frequency signal from passing between the first and second port terminals, respectively. A string of diodes is coupled between the common gate terminal and the first current terminal, and a common gate resistor is coupled between the common gate terminal and the switch control terminal. The diodes contribute to actively generating additional negative gate bias as RF power level increases.

Abstract: A passband filter includes a first and second microelectromechanical resonator system, each including a resonating beam, a drive electrode, and a sense electrode. An AC input signal is coupled to the drive electrode of the first and second microelectromechanical resonator system. A differential-to-single ended amplifier has a first input and second input respectively coupled to the sense electrodes of the first and second microelectromechanical resonator systems. An output of the differential-to-single ended amplifier is an output of the passband filter that provides a bandpass filtered signal of the AC input signal. A DC bias signal is coupled to the resonating beams of the first and second microelectromechanical resonator systems.

Abstract: In one aspect, an electronic device includes a switching circuit connected to a resistance circuit and ground, the resistance circuit connected to a port and the port configured to be connected in series to an external resistor and a supply voltage. A voltage at the port is a first voltage that is less than the supply voltage if the switching circuit is enabled to be a closed circuit and the voltage at the port is a second voltage that is equal to the supply voltage if the switching circuit is enabled to be an open circuit.

Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.

Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

Abstract: A driver circuit is configured to deliver drive signals from an output pin to a power switch to control ON/OFF switching of the power switch. A first detection pin of the driver circuit is configured to receive a first signal associated with the power switch, wherein the first signal indicates a voltage drop over the power switch and a voltage drop over one or more other circuit elements. A second detection pin is configured to receive a second signal, wherein the second signal indicates a voltage drop over one or more matched circuit elements, wherein the one or more matched circuit elements associated with the second signal are substantially identical to the one or more other circuit elements associated with the first signal. The driver circuit is configured to determine the voltage drop over the power switch based on a difference between the first signal and the second signal.

Abstract: A period from when switching elements S1, S4 at first diagonal positions in a full-bridge inverter are turned off at the same time to when switching elements S2, S3 at second diagonal positions are turned on at the same time, is defined as T1, and a period from when the switching elements S2, S3 at the second diagonal positions are turned off at the same time to when the switching elements S1, S4 at the first diagonal positions are turned on at the same time, is defined as T2. With a total length of T1 and T2 set to be constant, the lengths of T1 and T2 are controlled to be changed every switching cycle.

Abstract: Disclosed is a charge-pump phase-locked loop based on a unipolar thin film transistor, a chip, and a method. The phase-locked loop may include: a phase-frequency detector, configured to detect a phase difference and a frequency difference between a clock Fref and a clock Fn and generate control signals UP and DOWN; a logic control module, configured to output logic state signals; a charge pump, configured to convert the logic state signals into a charging/discharging current signal; a low-pass filter, configured to output a direct-current analog control signal Vctrl; a voltage-controlled oscillator, configured to adjust an output clock frequency Fvco; and a divide-by-four circuit, configured to perform frequency division to obtain the clock Fn.

Abstract: Embodiments of a differential bootstrapped track-and-hold circuit are disclosed. In an embodiment, the differential bootstrapped track-and-hold circuit includes first and second single-ended bootstrapped track-and-hold circuits. Each single-ended bootstrapped track-and-hold circuit includes a sampling switch connected between an input terminal and an output terminal, a sampling capacitor connected to the output terminal, and a dummy sampling switch connected between the input terminal and a dummy output terminal. The sampling switch and the dummy sampling switch are controlled by a bootstrap driver connected to the input terminal.

Abstract: Embodiments described herein provide foreign object detection based on coil current sensing. The transmitter power loss is computed directly based on the coil current, in conjunction with, or in place of the conventional computation based on transmitter input current. The enhanced precision of the computer power loss can be used to more accurately detect a foreign object near the transmitter coil during a wireless power transfer.

Abstract: A gate driver communication system includes a cored transformer including a primary coil and a secondary coil configured to receive power signals and uplink data signals from the primary coil; a primary side power signal generator coupled to the primary coil and configured to generate the power signals having a first frequency; a primary side data transmitter coupled to the primary coil and configured to generate the uplink data signals having a second frequency different from the first frequency; and a primary side controller configured to allocate the power signals and the uplink data signals to the primary coil according to a plurality of time slots, wherein the power signals are allocated to first time slots of the plurality of time slots and the uplink data signals are allocated to second times slots of the plurality of time slots.

Abstract: A device for hooking up a signal-outputting mechanism with two potential sensors each of which has allocated to it two evaluation terminals, wherein the potentials of the evaluation terminals depend inversely on the resistances between the respective evaluation terminals.

Abstract: An apparatus and a method that provide a bias voltage to a charge pump circuit are described. An example apparatus includes: a bias voltage generator that receives a first voltage and provides a second voltage responsive to the first voltage; a charge pump circuit that receives an input signal and provides the first voltage. The charge pump circuit includes an inverter and a bias transistor. The inverter receives the input signal and provides a third voltage. The bias transistor coupled between a power node having a power supply voltage and a slew rate driver of the inverter. The bias transistor receives the second voltage and provides a power supply voltage to the slew rate driver responsive to the second voltage less than a threshold voltage and stops providing the power supply voltage to the slew rate driver responsive to the second voltage greater than the threshold voltage.

Abstract: Provided is a driver circuit that controls an output unit that switches whether or not to supply a current to an output line, in accordance with a potential difference between a first control signal to be input and a voltage of the output line. The driver circuit comprises a control line that transmits the first control signal to the output unit; a low potential line to which a predetermined reference potential is applied; a first connection switching unit that switches whether or not to connect the control line and the low potential line, in accordance with a second control signal; and a cutoff unit that is provided in series with the first connection switching unit between the control line and the low potential line and cuts off the control line and the low potential line based on a potential of the low potential line.

Abstract: A semiconductor device includes: a pair of input terminals or receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path; a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween; a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

Abstract: A device for controlling a first voltage with a second voltage includes a first terminal of application of the second voltage and a second terminal for supplying the first voltage. A comparator has a first input terminal connected to the first terminal and has a second input terminal receiving information representative of the first voltage. At least one first current source of programmable intensity is connected to the second input terminal of the comparator.

Abstract: Systems and methods are described for active harmonics cancellation. A wireless charging apparatus includes a wireless-power transfer circuit comprising a wireless-power transfer coil configured to generate or couple to a magnetic field to transfer or receive power and a plurality of tuning capacitors electrically coupled to the wireless-power transfer coil. The apparatus also includes a power converter circuit electrically coupled to the wireless-power transfer circuit. Additionally, the apparatus includes a signal generation circuit different from the power converter circuit and electrically coupled to one or more nodes between capacitors of the plurality of tuning capacitors. The signal generation circuit is configured to generate and inject a signal into the wireless-power transfer circuit at the nodes between the capacitors. The signal generation circuit includes a rejection filter tuned to an operating frequency of the wireless-power transfer coil.

Abstract: According to one embodiment, a semiconductor integrated circuit device comprises first and second transistors having control terminals receiving an input signal and an inversion signal of the input signal, third and fourth transistors having control terminals receiving the input signal and the inversion signal, first and second inverters in which outputs are connected to inputs of other converters, and a fifth transistor connected to the first to fourth transistors. The third and fourth transistors are connected to outputs of the second and the first inverters. Clock signal is supplied to the fifth transistor.

Abstract: A circuit comprises an H-bridge circuit that includes a pair of current sources and a plurality of transistors. The H-bridge circuit includes a first output and a second output. One of the current sources is coupled to receive a supply voltage. A control circuit is configured to control, based on a sum of voltages on the first and second outputs, current of at least one of the current sources through at least some of the plurality of transistors.