Patents Examined by Colleen J O Toole
  • Patent number: 10727828
    Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 28, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventor: Lawrence A. Singer
  • Patent number: 10720919
    Abstract: Apparatus and methods for reducing charge injection mismatch are provided herein. In certain implementations, an electronic circuit includes one or more switch banks. Each switch bank can include a selection circuit and a plurality of switches that can be controlled using one or more clock signals. The selection circuit can select a first portion of the switches for operation in a first switch group and a second portion of the switches for operation in a second switch group. During a calibration, the electronic circuit's charge injection mismatch can be directly or indirectly observed for different switch configurations of the switch banks. The electronic circuit can be programmed to operate with the selected switch configurations of the switch banks to provide the electronic circuit with small charge injection mismatch.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: July 21, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Jie Zhou, Arthur J. Kalb
  • Patent number: 10715122
    Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Guolei Yu, Ajay Kumar Kosaraju, Marko Koski
  • Patent number: 10705558
    Abstract: Certain aspects of the present disclosure provide an input clock switching system, including: a clock source configured to output a reference clock signal; a clock generator circuit connected to the clock source and configured to output a plurality of input clock signals based on the reference clock signal; an output clock multiplexer, configured to: receive the plurality of input clock signals; receive an output clock selection signal; and output a first clock signal, wherein the first clock signal is one of the input clock signals; and a glitch suppression circuit, configured to: receive the first clock signal; receive a glitch suppression signal; output a clock output signal, wherein the clock output signal is: the first clock signal when the glitch suppression signal is in a first state; and a logic low signal when the glitch suppression signal is in a second state.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Huang, Nam Dang
  • Patent number: 10671911
    Abstract: Embodiments are directed to a driver circuit including a first amplifier having a voltage follower configured to control a first node to maintain a voltage of the first node at a constant value. By maintaining the first node voltage, the first amplifier having the voltage follower is further configured to have a first amplifier output current into the first node at a value without the effect of the voltage fluctuation. The driver circuit further includes a second amplifier configured to control a second node, wherein the second amplifier is in a current mirror configuration with respect to the first amplifier such that a second amplifier current output is a highly precise mirror of the first amplifier current output.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 2, 2020
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Patent number: 10666272
    Abstract: A COT control circuit for DC-DC converter. The COT control circuit has a synchronizing signal generator, an on time generator and a frequency locking circuit. The synchronizing signal generator generates a synchronizing signal and a frequency-modulated signal. The on time generator receives an input voltage signal, an output voltage signal, an error signal and the frequency-modulated signal to generate an on time signal. The error signal is generated by the frequency locking circuit based on the on time signal and the synchronizing signal. The operation frequency of a steady state of the DC-DC converter is regulated through changing the value of the frequency-modulated signal.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 26, 2020
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Lei Li
  • Patent number: 10659033
    Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 19, 2020
    Inventors: Sujan Kundapur Manohar, Michael James Mills, Justin Patrick Vogt
  • Patent number: 10643125
    Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 5, 2020
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Patent number: 10601423
    Abstract: A Low-Voltage Differential Signaling (differential signaling) driver circuit (10) comprising enable circuitry for enabling and disabling the differential signaling driver circuit (10) in accordance with an control signal is described. The differential signaling driver circuit (10) comprises: a differential output (12, 13) connected or connectable to a differential signaling receiver circuit via a differential transmission line; current control circuitry (14) for driving a signal current through the differential output (12, 13) in accordance with a driver signal; feedback circuitry (16) for driving the current control circuitry (14) to counteract a difference between a common mode voltage of the differential output (12, 13) and a reference voltage from a reference voltage provider; and the enable circuitry (18).
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: March 24, 2020
    Assignee: NXP USA, INC.
    Inventors: Alexey Michailovich Balashov, Andrey Evgenevich Malkov
  • Patent number: 10594299
    Abstract: The present disclosure provides an analog counter circuit for use in a minimal-sized circuitry. The analog counter circuit of the present disclosure can provide much higher resolution versus power consumption and layout area as compared to conventional digital counters. The analog counter circuit of the present disclosure can also provide much better bias supply management, step accuracy, multi-element step uniformity and lower supply spiking as compared to conventional analog counter architectures. The compact size of the disclosed counter circuit allows better integration of arrayed elements, such as, an array of image sensing pixels or an array of artificial neurons.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: March 17, 2020
    Inventors: Kenton Veeder, Aaron Bluestone, Christoph von Jutrzenka Trzebiatowski, Nishant Dhawan
  • Patent number: 10586796
    Abstract: A circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal. Each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device. The semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices. The switches are integrated in a common semiconductor body. The first switch is implemented in a first area of the semiconductor body, and the second switch is implemented in a second area. In a horizontal plane, the first area surrounds the second area.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventor: Rolf Weis
  • Patent number: 10574228
    Abstract: The signal multiplexer 1 inputs two selection signals CLK<1>, CLK<2> that sequentially reach significant levels, inputs two input signals IN<1>, IN<2>, and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN<m> of the two input signals when an m-th selection signal CLK<m> of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 25, 2020
    Inventors: Yusuke Fujita, Satoshi Miura, Shunichi Kubo
  • Patent number: 10548201
    Abstract: The power supply device includes a power switch including one terminal to which an input voltage is transferred; an inductor including one terminal connected to another terminal of the power switch; a diode connected between a ground and a floating ground; a sensing resistor connected between the floating ground and the one terminal of the inductor. A switch controller compares a modulation sensing voltage depending on a sensing voltage generated from the sensing resistor with a high peak reference and a low peak reference when a LED string is connected between an inductor and the ground. The switch controller controls a switching operation of a power switch according to the comparison result. The high peak reference and the low peak reference are references for controlling an upper limit and a lower limit of an LED current flowing through the LED string, respectively.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 28, 2020
    Inventors: Young-Je Lee, Gye-Hyun Cho, Jae-Yong Lee, Yoon-Woong Chung, Ji-Hoon Jang
  • Patent number: 10541683
    Abstract: A high-ohmic circuit includes a plurality of high-ohmic branches coupled in parallel between a first node and a second node. Each of the plurality of high-ohmic branches includes a first plurality of series connected resistive elements forming a first series path from the first node to the second node, each of the first plurality of series connected resistive elements comprising a first diode-connected transistor. Each of the plurality of high-ohmic branches further includes a second plurality of series connected resistive elements forming a second series path from the first node to the second node, each of the second plurality of series connected resistive elements comprising a second diode-connected transistor. The high-ohmic circuit further includes a plurality of switches, each of the switches being coupled between a corresponding one of the plurality of high-ohmic branches and the second node.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Cesare Buffa, Elmar Bach
  • Patent number: 10536139
    Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Shai Rotem, Norbert Unger, Michael Zelikson
  • Patent number: 10523211
    Abstract: A divider includes ? divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A ? divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: December 31, 2019
    Assignee: Silicon Laboratories Inc.
    Inventor: Brian G. Drost
  • Patent number: 10505526
    Abstract: A high frequency multichannel pulse width modulation (PWM) control apparatus includes a pre-scaler configured to divide a frequency of a main clock signal to generate a first clock signal, and a multichannel PWM generator including first to n-th PWM generators, the PWM generators comprising corresponding periods and duties, configured to generate, respectively, first to n-th PWM signals, through first and second N/2-bit counting for the main clock signal, using the first clock signal, wherein each of the first to n-th PWM generators performs the first N/2-bit counting on the main clock signal based on the first clock signal, a corresponding coarse duty value, and a corresponding coarse period value to generate a fine clock signal, and performs the second N/2-bit counting on the fine clock signal based on a corresponding fine duty value and a corresponding fine period value to generate a corresponding PWM signal.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 10, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jin Yong Kang
  • Patent number: 10432193
    Abstract: A switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common port and one or more user ports, any of which may be selectively coupled to the common port by closing an associated path switch; non-selected, unused ports are isolated from the common port by opening an associated path switch. Between each path switch and a port are associated split shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated split absorptive switch module. Each split absorptive switch module includes a split resistor coupled in parallel with a switch. The combination of the split resistor and the switch of the split absorptive switch module is placed in series with a corresponding signal path from each port to the common port.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 1, 2019
    Assignee: pSemi Corporation
    Inventor: Eric S. Shapiro
  • Patent number: 10418809
    Abstract: A power management integrated circuit includes pairs of high-side and low-side drivers, sensing circuitry, and a processor. The high-side and low-side drivers are used in combination with external discrete NFETs to drive multiple windings of a motor. The N-channel LDMOS transistor of each high-side driver has an associated isolation structure and a tracking and clamping circuit. If the voltage on a terminal of the integrated circuit pulses negative during a switching of current flow to the motor, then the isolation structure and tracking and clamping circuit clamps the voltage on the isolation structure and blocks current flow from the substrate to the drain. An associated ESD protection circuit allows the voltage on the terminal to pulse negative. As a result, a large surge of current that would otherwise flow through the high-side driver is blocked, and is conducted outside the integrated circuit through a body diode of an external NFET.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: September 17, 2019
    Assignee: Active-Semi, Inc.
    Inventor: Steven Huynh
  • Patent number: 10418899
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first threshold voltage and the second MOS transistor has a second threshold voltage where the first threshold voltage is less than the second threshold voltage.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 17, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Daniel S. Ng, Xiaobin Wang