Abstract: A pulse width modulation (PWM) method for converting an input signal into an output PWM signal includes the following steps: generating a first linear periodic wave and a second linear periodic wave which are triangle waves or sawtooth waves, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave; determining whether the level of the input signal is lower than a light load threshold; when the level of the input signal is lower than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the first linear periodic wave.

Abstract: An output driver is provided. The output driver includes: a pull-up driver connected between an output power supply voltage and an output node, and configured to pull up a voltage at the output node based on a pull-up driving signal and a pull-up reference voltage; a pull-down driver connected between the output node and a ground voltage, and configured to pull down the voltage at the output node based on a pull-down driving signal and a pull-down reference voltage; and a reference voltage compensation circuit configured to perform a short operation during transitions of the pull-up driving signal and the pull-down driving signal, wherein the short operation includes electrically connecting any one or any combination of the pull-up reference voltage to the ground voltage, and the pull-down reference voltage to the output power supply voltage.

Abstract: The present invention provides a drive module for a GaN transistor, including: a first pull-down transistor and a gate ringing and overshoot suppression unit, where the gate ringing and overshoot suppression unit and a first end of the first pull-down transistor are directly or indirectly connected to a gate of the GaN transistor, the gate ringing and overshoot suppression unit is connected between a second end of the first pull-down transistor and the ground; the gate ringing and overshoot suppression unit is configured to: when a gate voltage of the GaN transistor drops, control the release of a gate charge of the GaN transistor with a first impedance if the gate voltage is higher than a specified threshold; and control the release of the gate charge of the GaN transistor with a second impedance if the gate voltage is less than the specified threshold, where the first impedance is less than the second impedance.

Abstract: Systems and methods are described herein for controlling a switch. In some embodiments, circuitry may detect a voltage across the switch. A current reference signal may be generated based on the voltage across the switch. The switch may be controlled based, at least in part, on the current reference signal.

Abstract: A bootstrapped switch includes a sampling transistor, a bootstrapped circuit, and a buffer circuit. The sampling transistor is configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, in which a body of the sampling transistor is configured to receive a buffer signal. The bootstrapped circuit is configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor. The buffer circuit is configured to generate the buffer signal according to the input signal.

Abstract: A driving device comprises a first complementary metal-oxygen-semiconductor circuit and a first comparator. The first complementary metal-oxygen-semiconductor circuit is configured for outputting a power signal or a pull-down signal according to the first input signal. The first comparator comprises a first non-inverting input terminal and a first inverting input terminal. The first non-inverting input terminal is coupled to the first complementary metal-oxygen-semiconductor circuit, and is configured to receive the power signal or the pull-down signal. The first inverting input terminal is configured for receiving a first reference signal, and the first comparator is configured to compare one of the power signal and the pull-down signal and the first reference signal to provide a first driving signal.

Abstract: A comparator circuit according to this embodiment includes: a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit configured to hold a data of a data input terminal based on a comparator clock signal and configured to output an enable signal for stopping an operation of the comparator element; and an internal signal generation circuit configured to output an internal signal to the data input terminal based on the matching signal and an output signal output from the flip-flop circuit.

Abstract: A semiconductor device includes a first switch and a first driver. The first switch selects and outputs one of a power supply potential and a generated potential as a first switch output potential based on a synchronization signal from a transmission circuit and a delayed signal delayed from the synchronization signal. The first driver charges a gate of a bipolar transistor element based on the synchronization signal of the transmission circuit and the first switch output potential.

Abstract: An apparatus includes a transistor coupled to a load through an output terminal of a load switch IC, a gate drive circuit connected to a gate of the transistor, wherein the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the transistor is gradually reduced, and wherein as a result of reducing the voltage on the gate of the transistor gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.

Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.

Abstract: A field-effect transistor (FET) based synchronous rectifier for emulating a diode, comprising: a first terminal (20) and a second terminal (30); a first FET (M1) and a second FET (M2), wherein the second FET (M2) is adapted to control operation of the first FET (M1) to thereby allow unidirectional current flow when the two terminals (20, 30) are connected with an external circuit; and wherein the FET based synchronous rectifier comprises a fully integrated single-chip device (10) adapted to emulate a diode.

Abstract: A system for distributing DC bus voltage and control power to multiple motors includes a rectifier front end supplying a DC bus voltage and a DC control voltage. Both the DC bus voltage and the DC control voltage are distributed via a common set of conductors. Diodes are operatively connected between the DC control voltage and the common set of conductors. The diodes allow forward conduction of the DC control voltage and distribution of control power to distributed devices when the DC bus voltage is not present. Once the DC bus voltage is present, the diodes block conduction of the DC control voltage. Each of the distributed devices are configured with an internal power supply that is operative to generate an internal control voltage from either the DC control voltage or the DC bus voltage.

Abstract: The present disclosure relates to a power module with a power path extending through a first field-effect transistor (FET) and a second FET. A primary conductive structure connecting the first FET and the second FET in series provides a primary parasitic inductor within the power path. A first secondary conductive structure connected to both a gate and a source of the first FET provides a first secondary parasitic inductor within a first gate path, and a second secondary conductive structure connected to both a gate and a source of the second FET provides a second secondary parasitic inductor within a second gate path. The first secondary conductive structure and the second secondary conductive structure are configured such that mutual coupling between the first secondary parasitic inductor and the primary parasitic inductor and mutual coupling between the second secondary parasitic inductor and the primary parasitic inductor are substantially symmetrical.

Abstract: An electronic component is switched under the control of a pulse-width modulation signal. The electronic component outputs an output signal that is controlled by a control signal. The switching on or off is initiated within a pulse-width modulation cycle period at a level change time by a change of the pulse-width modulation signal. The control signal is set within each PWM cycle period to a first control value between the level change time and a first switching time, to a second control value between the first switching time and a second switching time, and to a third control value from the second switching time until a final gate-voltage value is reached on the gate of the electronic component. Each switching time of a PWM period is determined in dependence on an amplitude value determined during a preceding PWM cycle period, to limit amplitudes of the oscillation of the output signal.

Abstract: In a gate drive circuit of which an N-channel MOSFET and a P-channel MOSFET are connected in a push-pull manner to amplify an input pulse signal and drive an output element, a temperature correction circuit is connected between gate terminals of the N-channel MOSFET and the P-channel MOSFET. The temperature correction circuit lowers each of gate voltages of the N-channel MOSFET and the P-channel MOSFET as ambient temperature rises.

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.

Abstract: A capacitor-insulated semiconductor relay includes an RC oscillation circuit, a waveform regulation circuit, a booster circuit, a charging/discharging circuit, and an output circuit. The RC oscillation circuit generates first and second signals that are inverse in phase to each other. The waveform regulation circuit increases rise and fall times of the first signal, and rise and fall times of the second signal. Output signals from the waveform regulation circuit are respectively inputted to first and second high dielectric strength capacitors and that are provided in the booster circuit and connected in parallel to each other. The booster circuit receives the output signals from the waveform regulation circuit to generate a predetermined voltage. The output circuit is driven based on the predetermined voltage.

Abstract: A semiconductor device includes a main bi-directional switch formed on a semiconductor substrate and having first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain. The semiconductor device further includes a discharge circuit having a plurality of individual transistors or an auxiliary bi-directional switch monolithically integrated with the main bi-directional switch and connected in a common source configuration to the semiconductor substrate. The plurality of individual transistors or the auxiliary bi-directional switch includes a first drain connected to the first source of the main bi-directional switch, a second drain connected to the second source of the main bi-directional switch, and first and second gates each decoupled from gate drive circuitry so that the first and the second gates are controlled at least passively and based on a state of the main bi-directional switch.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.