Abstract: A read circuit for a memory cell may include an integrated logic circuit for sensing a current change. The integrated logic sensing circuit may be an offset cancelling single ended integrated logic sensing circuit. The circuit may include an offset canceling single ended sensing circuit coupled to a supply voltage, an offset canceling single ended sense amplifier circuit having a sense amplifier input coupled to the offset canceling single ended sensing circuit and a sense amplifier output, and a cell array coupled to a sensing circuit output and a ground.

Abstract: A nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a CSL driver, and control logic. The memory cell array includes a plurality of memory blocks each having a plurality of strings that are formed in a direction perpendicular to a substrate and are connected between bit lines and a common source line. The CSL driver sets up the common source line with a predetermined voltage and supplies or drains charge to or from the common source line using a voltage level of the common source line as a feedback signal.

Abstract: A phase change memory (PCM), a writing method thereof and a reading method thereof are provided. The PCM has a plurality of memory cells. The writing method comprises the following steps. At least one stress pulse is applied for aging at least one of the memory cells. A starting pulse is applied to all of the memory cells of the PCM for decreasing a resistance of each memory cell. A detection pulse is applied to all of the memory cells of the PCM for detecting the resistance of each memory cell. A set pulse is applied to the aged memory cells. A reset pulse is applied to the non-aged memory cells.

Abstract: A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, a decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.

Abstract: A memory cell includes a gate, a channel material having a channel surface and a channel valence band edge, and a dielectric stack between the gate and the channel surface. The dielectric stack comprises a multi-layer tunneling structure on the channel surface, a first charge storage nitride layer on the multi-layer tunneling structure, a first blocking oxide layer on the first charge storage nitride layer, a second charge storage nitride layer on the first blocking dielectric layer, and a second blocking oxide layer on the second charge storage nitride layer. The multi-layer tunneling structure includes a first tunneling oxide layer, a first tunneling nitride layer on the first tunneling oxide layer, and a second tunneling oxide layer on the first tunneling nitride layer.

Abstract: A repair circuit includes a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal, a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal when the partial input addresses and the partial repair addresses correspond to each other, and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal.

Abstract: A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is programmed to at least a second threshold voltage to indicate the particular data value. The second threshold voltage is greater than the first threshold voltage.

Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.

Abstract: A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

Abstract: Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Abstract: A non-volatile memory circuit includes an SRAM cell with magnetoelectric or ferroelectric structures for maintaining data within the SRAM cell even with power off. In some implementations, the magnetoelectric and ferroelectric structures can be programmed using a NOR or tristate gate coupled to an internal state of the SRAM cell. In other implementations, the magnetoelectric and ferroelectric structures can be configured as programmable resistors in the cross-coupled signal path of the SRAM inverters.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament; and a control circuit configured to execute a write sequence that writes data to the memory cell, the write sequence including: a setting operation that applies a setting pulse having a first polarity to the memory cell; and a removing operation that applies a removing pulse having a second polarity opposite to the first polarity to the memory cell; and the control circuit, during execution of the write sequence, is configured to repeatedly execute the setting operation until the memory cell attains a desired data storing state, and then to execute the removing operation.

Abstract: A memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result.

Abstract: A semiconductor memory apparatus includes an internal data generation block configured to generate test data in response to test signals, and output ones of normal data inputted from data input/output pads and the test data as internal data according to a test flag signal; a data storage region configured to receive and store the internal data, and output stored data as cell storage data; a latch block configured to receive and store the cell storage data in response to a data output enable signal, and output stored data as latch data; and a data comparison block configured to compare the test data and the latch data, and generate a test result signal.

Abstract: A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit through the selection circuit. The data line is electrically connected to the flip-flop circuit. The bit line is electrically connected to the nonvolatile memory circuit through the selection circuit. The selection circuit selectively stores data based on a potential of the data line or a potential of the bit line in the nonvolatile memory circuit.

Abstract: A memory element has a layered structure, including a memory layer that has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a Co—Fe—B magnetic layer, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, a magnetization-fixed layer having magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, a first oxide layer and a second oxide layer.

Abstract: A circuit can include at least one two terminal element programmable between at least two impedance states; a write section configured to place the element into different impedance states in a write mode; and a read section configured to generate an output value corresponding to the impedance state of at least one element in a read mode; wherein the at least one element draws substantially no current in a standard mode that is different from the write and read modes.