Abstract: A semiconductor memory apparatus may include a memory bank having a plurality of memory cell arrays. The memory bank may have an open bit line structure. A sense amplifier array may be coupled in common with adjacent memory cell arrays. A sense amplifier coupled in common with a dummy array and a normal array may be coupled with one bit line disposed in the normal array and two bit lines disposed in the dummy array.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Abstract: An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit.

Abstract: A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.

Abstract: A semiconductor memory device includes a plurality of memory cells and an X-decoder. The plurality of memory cells are connected to a word line. The X-decoder is connected to the word line, and applies an operating voltage to the word line. In the semiconductor memory device, tunnel insulating layers included in the plurality of memory cells have different thicknesses according to distances of the plurality of memory cells from the X-decoder.

Abstract: A data storage device includes a nonvolatile memory device including: memory cells of a first area grouped by page, and memory cells of a second area respectively corresponding to pages, and suitable for storing information representing whether each page of the first area is in an erased state; and a controller suitable for providing the nonvolatile memory device with a search command for searching an erased page and a search address of a page, wherein the nonvolatile memory device provides the controller with a state of at least one memory cell of the second area corresponding to the search address in response to the search command.

Abstract: A one-time memory control apparatus is obtained that prevents erroneous opening of a fuse from causing logic conversion and enhances the reliability. The one-time memory control apparatus includes an opening current creation fuse C opening switch and an opening current creation fuse D opening switch that each allow a fuse opening current from a fuse opening current creation circuit to flow in response to an opening enable signal, and a fuse opening permission signal creation circuit that receives respective logic signals corresponding to the states of fuse opening currents that flow through an opening current creation fuse C and an opening current creation fuse D, and that creates a fuse opening permission signal.

Abstract: A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.

Abstract: A method for writing data into a flash memory unit includes: when writing data into the flash memory unit for the n-th time, determining a data polarity of an n-th data bit to be written into the flash memory unit; selectively injecting an n-th electrical charge amount into a floating gate of the flash memory unit according to the data polarity of the n-th data bit; when writing data into the flash memory unit for the (n+1)-th time, determining the data polarity of an (n+1)-th data bit to be written into the flash memory unit; and selectively injecting an (n+1)-th electrical charge amount into the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit. The (n+1)-th electrical charge amount is not equal to the n-th electrical charge amount, and n is a positive integer not less than 1.

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

Abstract: A highly reliable semiconductor device. In a configuration where a precharged source line is discharged to a bit line by establishing electrical continuity between the source line and the bit line through a transistor to read a potential retained at a gate of the transistor, the potential of the bit line is switched in accordance with a change in potential of the source line due to the discharge. With this configuration, the voltage between the source and drain of the transistor can be kept lower than a predetermined voltage by discharge. Accordingly, the source-drain voltage of the transistor can be kept lower than its breakdown voltage, so that the semiconductor device can have high reliability.

Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

Abstract: A circuit for control of time for read operation is disclosed which additionally incorporates a dummy device circuit and a dummy sensitive amplifier circuit, uses a current mirror circuit to mirror a reference current in a reference device circuit into the dummy device circuit to generate a mirrored current, and generates time control signals based on the mirrored current. Due to the same adaptation of the mirrored current to the size of a test device as the reference current, the time control signals are also adapted to the size of the test device. This addresses the problem of fixed time control signals arising from the use of a conventional RC relay circuit and enables the time control signals to change with the size of the test device as well as Process Voltage Temperature, thereby resulting in an effective reduction in average energy consumed in read operation.

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Abstract: A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a plurality of signal lines, and a second switch unit including a pair of switches arranged in correspondence to the at least one pair of switches of the first switch unit. A first pair of switches of the first switch unit includes a first switch and a second switch that are of the same type, and a second pair of switches of the second switch unit includes a third switch and a fourth switch that are connected to the first pair of switches. A selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.

Abstract: An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage.

Abstract: A circuit includes a latch circuit, a buffer transistor having a control terminal coupled to a first output of the latch, a first write transistor having a conduction terminal coupled to the first output and a control terminal coupled to a first write bitline, and a second write transistor having a conduction terminal coupled to a second output of the latch and a control terminal coupled to a second write bitline. A method of operating a memory cell circuit includes providing a first value on first and second write bitlines when a read operation is performed, and when a write operation is performed, providing first and second values on the first and second write bitlines, respectively, when a first storable value is to be stored, and providing the first and second value on the second and first write bitlines, respectively, when a second storable value is to be stored.