Patents Examined by Courtney A. Bowers
  • Patent number: 5751018
    Abstract: Methods are described for attaching semiconductor nanocrystals to solid inorganic surfaces, using self-assembled bifunctional organic monolayers as bridge compounds. Two different techniques are presented. One relies on the formation of self-assembled monolayers on these surfaces. When exposed to solutions of nanocrystals, these bridge compounds bind the crystals and anchor them to the surface. The second technique attaches nanocrystals already coated with bridge compounds to the surfaces. Analyses indicate the presence of quantum confined clusters on the surfaces at the nanolayer level. These materials allow electron spectroscopies to be completed on condensed phase clusters, and represent a first step towards synthesis of an organized assembly of clusters. These new products are also disclosed.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: May 12, 1998
    Assignee: The Regents of the University of CAlifornia
    Inventors: A. Paul Alivisatos, Vicki L. Colvin
  • Patent number: 5679964
    Abstract: The optoelectronic integrated device includes a semiconductor substrate, a vertical-cavity surface-emitting semiconductor laser formed on the semiconductor substrate, a phototransistor stacked over the vertical-cavity surface emitting semiconductor laser, for driving the vertical-cavity surface-emitting semiconductor laser, and a semiconductor buffer structure interposed between the vertical-cavity surface-emitting semiconductor laser and the phototransistor. The vertical-cavity surface-emitting semiconductor laser includes: a bottom semiconductor mirror; a top semiconductor mirror; and an active region interposed between the bottom semiconductor mirror and the top semiconductor mirror and having a strained quantum well structure for emitting light having a wavelength of .lambda.. The phototransistor includes: a collector layer; an emitter layer; and a base layer interposed between the collector layer and the emitter layer and absorbing light having a wavelength of .lambda..
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: October 21, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Kobayashi, Kenichi Matsuda
  • Patent number: 5675170
    Abstract: A data output buffer is disclosed. Generation of a latch-up is prevented by forming a N-well guard ring to interrupt the movement of minority carriers injected from the drain of NMOS transistor to the N.sup.+ pickup region of PMOS transistor. Accordingly, reliability of the device is improved.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 7, 1997
    Assignee: Hyndai Electronics Industries, Co., Ltd.
    Inventor: Pil Jong Kim
  • Patent number: 5663572
    Abstract: An optical functional semiconductor element which performs ultrafast, high-contrast logic operation through utilization of the high speed of light velocity. A resonant-tunneling diode having a negative resistance characteristic is provided apart from a light absorbing layer formed by one of i-type layers of what is called a triangular barrier diode of an nipin or pinip structure, by which as the quantity of incident light increases, the quantity of transmitted current is switched from increase to decrease, the amount of change is made high-contrast and an ultrafast logic operation can be performed.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: September 2, 1997
    Assignee: Kokusai Denshin Denwa Kabushiki Kaisha
    Inventors: Haruhisa Sakata, Katsuyuki Utaka, Yuichi Matsushima
  • Patent number: 5646437
    Abstract: The light receiving or back-side surface (22) of an indium antimonide (InSb) photodetector device (10) substrate (12) is cleaned to remove all native oxides of indium and antimony therefrom. A passivation layer (26) is then formed on the surface (22) of a material such as silicon dioxide, silicon suboxide and/or silicon nitride which does not react with InSb to form a structure which would have carrier traps therein and cause flashing. The device (10) is capable of detecting radiation over a continuous spectral range including the infrared, visible and ultraviolet regions.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: July 8, 1997
    Assignee: Santa Barbara Research Center
    Inventors: Ichiro Kasai, John R. Toman
  • Patent number: 5640039
    Abstract: A method and apparatus for providing a conductive plane beneath a suspended microstructure. A conductive region is diffused into a substrate. A dielectric layer is added, covering the substrate, and then removed from a portion of the conductive region. A spacer layer is deposited over the dielectric and exposed conductive region. A polysilicon layer is deposited over the spacer layer, and formed into the shape of the suspended microstructure. After removal of the spacer layer, the suspended microstructure is left free to move above an exposed conductive plane. The conductive plane is driven to the same potential as the microstructure.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: June 17, 1997
    Assignee: Analog Devices, Inc.
    Inventors: Kevin Hin-Leung Chau, Roger T. Howe, Richard S. Payne, Yang Zhao, Theresa A. Core, Steven J. Sherman
  • Patent number: 5637910
    Abstract: A transistor includes (a) a first semiconductor layer formed by a semiconductor substrate; (b) a second semiconductor layer formed on the first semiconductor layer and having an impurity of the same conductivity type as the first layer in a concentration lower than that of the first semiconductor layer; and (c) a third semiconductor layer formed on the second semiconductor layer having an impurity of the same conductivity type as the first semiconductor layer in a concentration lower than that of the second semiconductor layer. A base region is formed in the third layer and an emitter region is formed in the base region.
    Type: Grant
    Filed: February 1, 1995
    Date of Patent: June 10, 1997
    Assignee: Rohm Co., Ltd.
    Inventor: Kazuhisa Sakamoto
  • Patent number: 5635745
    Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: June 3, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Wolfgang K. Hoeld
  • Patent number: 5616937
    Abstract: A compound semiconductor luminescent device is disclosed which comprises a semiconductor substrate and a multi-layered structure disposed on the substrate, the multi-layered structure comprising at least one conductive layer, a luminescent layer, and a current injection layer, wherein the substrate and the layers are made of at least one kind of II-VI group compound semiconductor.
    Type: Grant
    Filed: July 30, 1991
    Date of Patent: April 1, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiko Kitagawa, Yoshitaka Tomomura
  • Patent number: 5615027
    Abstract: A liquid crystal apparatus, includes: a) a liquid crystal device comprising an electrode matrix composed of scanning electrodes and data electrodes, and a ferroelectric liquid crystal showing a first and a second orientation state; and b) a driving means including: a first drive means for applying a scanning selection signal to the scanning electrodes two or more scanning electrodes apart in one vertical scanning so as to effect one picture scanning in plural times of vertical scanning, said scanning selection signal having a voltage of one polarity and a voltage of the other polarity with respect to the voltage level of a nonselected scanning electrode, and a second drive means for applying to a selected data electrode a voltage signal which provides a voltage causing the first orientation state of the ferroelectric liquid crystal in combination with the voltage of one polarity of the scanning selection signal, and applying to another data electrode a voltage signal which provides a voltage causing the secon
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: March 25, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaki Kuribayashi, Yukiko Futami, Hiroshi Inoue, Akira Tsuboyama, Yutaka Inaba
  • Patent number: 5610425
    Abstract: An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line V.sub.SS. The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: March 11, 1997
    Assignee: Motorola, Inc.
    Inventors: John H. Quigley, David F. Mietus
  • Patent number: 5602403
    Abstract: A buried, gate insulator field effect transistor is disclosed. It comprises a source, drain, substrate, gate, and a gate insulator layer separating the gate from the source, drain and substrate; and a protective silicon dioxide covering layer. Windows are excised into this covering layer to allow electrical connection to the source, substrate, drain, and gate. The substrate and gate are vertically aligned in the resulting structure. The source, drain and gate are fabricated from a doped, semiconductor of one polarity while the substrate is fabricated from doped semiconductor of the opposite polarity. The gate insulator layer is fabricated by implanting an element or elements selected from Group V, VI or VII into the semiconductor to form a semiconductor-compound insulator. Methods of fabricating this device are also disclosed. In one embodiment the device is fabricated on top of an insulating support. The gate is formed next to the base. In a second embodiment, no base is used.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: February 11, 1997
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Monti E. Aklufi
  • Patent number: 5596207
    Abstract: A technique for quantifying the effect of plasma/etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: January 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Srikanth Krishnan, Jeffrey A. McKee
  • Patent number: 5594259
    Abstract: A semiconductor device includes an insulating substrate; and an electrode wiring provided on an area of the insulating substrate. The electrode wiring is formed of a material selected from the group consisting of an alloy of Ta and Nb, Nb, and a metal mainly including Nb. A method for producing a semiconductor device includes the steps of forming a layer including Nb doped with nitrogen on an insulating substrate by a sputtering method in an atmosphere of an inert gas including nitrogen, and then patterning the layer to form an electrode wiring on an area of the insulating substrate; and forming an oxide film at a portion of the electrode wiring by anodization, the portion including at least a surface thereof.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: January 14, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasunori Shimada, Masahito Goto, Hisashi Saito, Koji Taniguchi
  • Patent number: 5592003
    Abstract: The promotion of reduction of the power source voltage for use in a nonvolatile semiconductor memory is attained by using a method wherein memory cells each of which includes a control gate having a floating gate above a channel region, and a source constituted by an N-type impurity diffusion layer enclosed with a high impurity concentrated P-type diffusion layer containing impurities the impurity concentration of which is higher than that of a P-type well are formed in double wells made up of an N-type well and the P-type well which are formed in a P-type silicon substrate, the electric potentials at the N-type well and the P-type well are controlled independently to each other to write data to the memory cell by utilizing the tunnel phenomenon, the electrical potential at the P-type well is made negative, and under this condition, a relatively low positive voltage and a high voltage are respectively applied to the control gate and the source and the hot electrons generated in the vicinity of the source are
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: January 7, 1997
    Assignee: Nippon Steel Corporation
    Inventors: Yasuo Sato, Kikuzo Sawada
  • Patent number: 5591999
    Abstract: A semiconductor memory device according to the present invention comprises a plurality of electrically rewritable memory cells, each of which contains a drain and a source, at least one source line coupled to the sources of the memory cells through a contact hole, and bit lines arranged so as to avoid the contact hole.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: January 7, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Momodomi, Junichi Miyamoto, Toshiharu Watanabe
  • Patent number: 5589705
    Abstract: Semiconductor radial rays detector is provided that improves a breakdown voltage yield of a gate insulating film of a semiconductor radial rays detector and prevents an increase in resistance of a gate electrode caused by the improvement in the breakdown voltage yield. In the inventive semiconductor radial rays detector, material used as a gate electrode 1 of a reading condenser is not an Al film (aluminum film) but a POLY Si film (a polycrystalline silicon film), or silicide or metal including silicide with a high melting point such as WSi (tungsten silicide) (strictly its composition is indefinite as expressed as W.sub.x Si.sub.y) or TiSi (titan silicide) (expressed as Ti.sub.x Si, in the same manner). Further, a contact hole 2 is provided on the gate electrode 1 through an inter-insulating film 4 as the inter-insulating film for wiring, and an Al electrode 3 coupled to an output terminal is provided over the contact hole.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: December 31, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saito, Yoshikazu Kojima
  • Patent number: 5585658
    Abstract: In implantation of ions into a wafer, in the manufacture of a semiconductor device, a desired ion beam absorber pattern having locally different thicknesses is previously formed on a major surface of the wafer. The ion beam absorber pattern absorbs an ion beam to be implanted and is formed of a thin film material with its absorbency varying depending on its thickness. Ions are implanted once on the major surface of the wafer through this ion beam absorber pattern to form desired different impurity profiles in depth of desired regions on the major surface of the wafer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 17, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Mukai, Nobuyuki Yoshioka
  • Patent number: 5581092
    Abstract: In order to provide TFTs having a low leak current property in its reverse biased state, the active semiconductor layer of the TFTs is doped with an impurity for increasing the band gap thereof, for example, carbon, nitrogen, and oxygen. Also, in order to compensate the decrease in conductivity due to the addition of the impurities, the source and drain regions are provided with or are by themselves formed with metal silicide layers. Further, these low leak current TFTs formed on a substrate are used as pixel transistors in an electro-optical device while peripheral circuits are formed on the same substrate using high mobility TFTs.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: December 3, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 5578862
    Abstract: By reverse biasing the PN junction formed around a semiconductor element, the semiconductor element is isolated from other elements. The PN junction around the semiconductor element is a junction between a layer surrounding the semiconductor element and a layer disposed outside the layer. Jointly with the layer constituting the semiconductor, the layer surrounding the semiconductor element forms a parasitic diode. The potential of the layer on the semiconductor element to be connected to the layer surrounding the semiconductor element is detected, and based on this potential, the voltage to be applied to the parasitic diode is controlled so as to be constant. When the voltage to be applied to the parasitic diode is lower than a threshold, the parasitic diode will be in a cutoff state.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: November 26, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuo Fujii, Yosuke Mizukawa, Yasuo Mitsuhashi