Patents Examined by Courtney A. Bowers
  • Patent number: 5578847
    Abstract: A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: November 26, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masami Aoki, Takashi Yamada, Hiroshi Takato, Tohru Ozaki, Katsuhiko Hieda, Akihiro Nitayama
  • Patent number: 5576555
    Abstract: A thin film semiconductor device includes a gate electrode, a gate insulating electrode, a thin film semiconductor layer, an ohmic layer, source and drain electrodes, and a protective layer. The protective layer contains an impurity for controlling conductivity.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: November 19, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masato Yamanobe, Takayuki Ishii
  • Patent number: 5574298
    Abstract: A method for forming a gate array substrate contact and the contact resulting therefrom includes the steps of etching off polysilicon gate layers at the same time as cutting the polysilicon to form the gate array base cell (10). The method includes forming openings (40, 42, and 44) in the second insulating layer (34) and insulating layer (30) to connect a lead (46, 48, and 50) to the underlying substrate.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: November 12, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Louis N. Hutter, S. Shivaling Mahant-Shetti
  • Patent number: 5572054
    Abstract: A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the source region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: November 5, 1996
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Ping Wang, Bing Yeh
  • Patent number: 5567979
    Abstract: A buffer layer having crystal orientation in a (111) face is formed on a semiconductor single-crystal (100) substrate and a ferroelectric thin film having crystal orientation in a (111) or (0001) face is then formed over the buffer layer. The buffer layer is preferably formed of MgO at a temperature ranging from 20 to 600.degree. C. and at a rate ranging from 0.5 to 50 .ANG./sec. The thus formed ferroelectric thin film has its axes of polarization aligned in one direction. Using the oriented ferroelectric thin-film device, highly functional nonvolatile memories, capacitors or optical modulators can be fabricated on semiconductor substrates.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: October 22, 1996
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Keiichi Nashimoto, Atsushi Masuda
  • Patent number: 5563438
    Abstract: A rugged MOS output stage transistor having a third region formed adjacent to the drain region on the side opposite the source. The third region is doped to have a polarity opposite the drain and forms in combination with the drain an output protect diode which renders the transistor relatively free of latch-up. The concept of the third region of opposite polarity adjacent to the drain may be used in both NMOSFET and PMOSFET as well as CMOS output stages.
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: October 8, 1996
    Assignee: AlliedSignal Inc.
    Inventor: Joseph C. Tsang
  • Patent number: 5561302
    Abstract: An enhanced mobility MOSFET device (10) comprises a channel layer (12) formed on a monocrystalline silicon layer (11). The channel layer (12) comprises an alloy of silicon and a second material with the second material substitutionally present in silicon lattice sites at an atomic percentage that places the channel layer (12) under a tensile stress.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: October 1, 1996
    Assignee: Motorola, Inc.
    Inventor: Jon J. Candelaria
  • Patent number: 5559619
    Abstract: A liquid crystal electro-optical device having gettering means therein and a method for manufacturing such a liquid crystal electro-optical device are disclosed. For example, in a liquid crystal panel disposed in the device, polyvinyl carbazole film is formed as the getting means on at least one of a pair of substrates, and the film has a function to absorb ionized impurities existing in liquid crystal disposed in the device. In virtue of the film, ionized impurities in the liquid crystal layer are decreased, and by heating the liquid crystal panel, the function of the polyvinyl carbazole film, i.e. the function to absorb ionized impurities, is enhanced. Consequently, a liquid crystal electro-optical device free from after-image which was a problem in conventional liquid crystal display devices can be obtained.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: September 24, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masahiko Sato
  • Patent number: 5559344
    Abstract: A thin-film semiconductor device includes a plurality of thin-film semiconductor elements each having a gate electrode formed on a substrate, an insulating film formed on the gate electrode, a semiconductor film formed on the insulating film and doped with an n-type impurity, and source and drain electrodes formed on the semiconductor film and separated from each other, that region of the semiconductor film which corresponds to a gap between the source electrode and the drain electrode, being doped with a p-type impurity so that the p-type impurity concentration is equal to or greater than the n-type impurity concentration, to form an intrinsic layer, scanning-signal transmitting electrode lines each formed so as to connect the gate electrodes of some of the thin-film semiconductor elements, video-signal transmitting electrode lines each formed so as to connect the drain electrodes of some of the thin-film semiconductor elements, and pixel electrodes each connected to the source electrode of one of the thin-f
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: September 24, 1996
    Assignee: Hitachi, Ltd.
    Inventor: Genshiro Kawachi
  • Patent number: 5557117
    Abstract: A heterojunction bipolar transistor includes a collector contact layer constituted by a high-concentration first semiconductor layer of a first conductivity type formed on a semiconductor substrate, a collector region stacked on the collector contact layer, a base layer constituted by a fifth semiconductor layer of a second conductivity type formed on the collector region, and an emitter layer constituted by a semiconductor layer of the first conductivity type formed on the base layer.
    Type: Grant
    Filed: May 11, 1994
    Date of Patent: September 17, 1996
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yutaka Matsuoka, Eiichi Sano, Kenji Kurishima, Hiroki Nakajima, Tadao Ishibashi
  • Patent number: 5554872
    Abstract: In a semiconductor device including a composite substrate formed by bonding first and second semiconductor substrates to each other through an oxide film and an insulator isolation trench formed from a major surface of the first semiconductor substrate to reach the oxide film and to surround an element forming region, when the potential of the second substrate is set at a potential higher than the minimum potential in the element forming region of the first substrate, an breakdown voltage can be increased. In a semiconductor integrated circuit having an element isolation region, a semiconductor device of a perfect dielectric isolation structure having an element forming region having a thickness smaller than that of the element forming region of a P-N junction isolation structure is used to reduce, e.g., a base curvature influence, thereby obtaining a further high breakdown voltage.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: September 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiro Baba, Shunichi Hiraki, Akihiko Osawa
  • Patent number: 5554875
    Abstract: A semiconductor device with a force and/or acceleration sensor (12), which has a spring-mass system (14, 16) responsive to the respective quantity to be measured and whose mass (16) bears via at least one resilient support element (14) on a semiconductor substrate (20). The semiconductor substrate (20) and the spring-mass system (14, 16) are integral components of a monocrystalline semiconductor crystal (10) with a IC-compatible structure. The three-dimensional structural form of the spring-mass system (12) is produced by anisotropic semiconductor etching, defined P/N junctions of the semiconductor layer arrangement functioning as etch stop means in order to more particularly create a gap (22) permitting respective movement of the mass (16) between the mass (16) and the semiconductor substrate (20).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 10, 1996
    Assignee: Texas Instruments Deutschland
    Inventor: Siegbert Hartauer
  • Patent number: 5552620
    Abstract: There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: September 3, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Yuan Lu, Horng-Huei Tseng
  • Patent number: 5552624
    Abstract: The electronic component comprises, topologically integrated within the same semiconductor structure (1), a first semiconductor area (12, 13, 3, 4, 20) capable of forming an insulated-gate field-effect transistor, and a second semiconductor area (12, 20, 18, 19, 11) capable of forming a lateral bipolar transistor, the two areas having a common semiconductor layer (20) in which the channel of the field-effect transistor is capable of being formed and/or the base current of the bipolar transistor is capable of flowing, the two areas being capable together of forming a structure capable of negative dynamic resistance.
    Type: Grant
    Filed: July 2, 1993
    Date of Patent: September 3, 1996
    Assignee: France Telecom
    Inventors: Tomasz Skotnicki, Gerard Merckel
  • Patent number: 5550388
    Abstract: A heterojunction FET disclosed herein includes a semi-insulating GaAs substrate, a buffer layer composed of an undoped In.sub.y/2 Al.sub.1-y/2 As layer (0<y<1), and having a film thickness less than or equal to a critical film thickness, a first barrier layer composed of an undoped AlAs layer and an undoped In.sub.y Al.sub.1-y As layer (0<y<1), a channel layer composed of an undoped In.sub.y Ga.sub.1-y As layer (0<y<1), a second barrier layer composed of an N-type In.sub.y Al.sub.1-y As layer (0<y<1), each layer disposed in the order mentioned, on the semi-insulating GaAs substrate, a gate electrode which is selectively disposed on the second barrier layer to form a Schottky junction, and electrodes for a drain and a source, each of which is disposed on the second barrier layer via a contact layer, with said gate electrode therebetween.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: August 27, 1996
    Assignee: NEC Corporation
    Inventor: Junzi Haruyama
  • Patent number: 5548136
    Abstract: The invention provides a semiconductor substrate comprising a substrate of a first material and a crystal growth layer formed on the substrate, the crystal growth layer being made of compound semiconductors different from the first material wherein the substrate has a surface diffusion region being heavily doped with one or more elements of the compound semiconductors. A silicon substrate receives an ion-implantation of one or more elements constituting a compound semiconductor different except for silicon at a high impurity concentration for a heat treatment at a higher temperature than a growth temperature of the compound semiconductor and subsequent cooling down to the growth temperature of the compound semiconductor followed by crystal growth of the compound semiconductor on the substrate.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: August 20, 1996
    Assignee: NEC Corporation
    Inventor: Shuji Asai
  • Patent number: 5543654
    Abstract: A Fermi-threshold field effect transistor includes a contoured-tub region of the same conductivity type as the source, drain and channel regions and having nonuniform tub depth. The contoured-tub is preferably deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. The diffusion capacitance is thereby reduced compared to a tub having a uniform tub depth, so that a high saturation current is produced at low voltages. The contoured-tub may be formed by an additional implant into the substrate using the gate as a mask.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: August 6, 1996
    Assignee: Thunderbird Technologies, Inc.
    Inventor: Michael W. Dennen
  • Patent number: 5541434
    Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: July 30, 1996
    Assignee: Inmos Limited
    Inventors: Howard C. Nicholls, Michael J. Norrington
  • Patent number: 5541440
    Abstract: It is an object of the present invention to provide a semiconductor device which has a high electrical isolation capability and an enhanced electrical reliability for avoiding short circuit of individual conductive layers, and the present invention also provides a method of manufacturing such a semiconductor device. An n.sup.+ buried layer and an n.sup.- epitaxial growth layer are formed on a p.sup.- silicon substrate. An element isolation oxide film having a through hole is formed on the surface of n.sup.- epitaxial growth layer. A trench which penetrates through n.sup.- epitaxial growth layer and n.sup.+ buried layer to reach a predetermined depth of p.sup.- silicon substrate is formed under through hole. A first insulating layer covers the internal wall of trench. A covering layer covers the sidewall of through hole. A filling layer is formed to fill trench so that the top surface thereof is located within through hole. A second insulating layer is formed on filling layer.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: July 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Kozai, Kiyoto Watabe, Tatsuhiko Ikeda
  • Patent number: 5541438
    Abstract: An improved Metal Semiconductor Metal (MSM) photodiode device and a fabrication process for realizing this device. The improved photodiode device employs frontside electrodes and backside illumination to avoid active area shadowing in the device. This configuration is achieved through a device fabrication sequence which involves substrate removal--and replacement at the device's opposed frontside surface using such media as an epoxy adhesive. The disclosed device uses gallium arsenide semiconductor materials that are lattice determined by an indium phosphide sacrificial initial substrate, in order to select a desired input energy spectral range.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: July 30, 1996
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Eric A. Martin, Kenneth Vaccaro, Joseph P. Lorenzo