Abstract: An organic light-emitting display apparatus implemented by using a plurality of organic light-emitting diodes on a substrate and including a first pixel and a second pixel respectively emitting light of different colors, includes: a pixel-defining layer including a first opening and a second opening, the first opening defining an emission area of the first pixel, and the second opening defining an emission area of the second pixel; a total reflective layer over the pixel-defining layer, the total reflective layer including a first upper opening corresponding to the first pixel and a second upper opening corresponding to the second pixel; and a planarization layer covering the total reflective layer and having a refractive index greater than a refractive index of the total reflective layer, wherein an area of the first upper opening is different from an area of the second upper opening.

Abstract: A Fin-FET device is provided. The Fin-FET device includes a semiconductor substrate, a fin structure formed on the semiconductor substrate having a core region and two peripheral regions separated by the core region; a plurality of metal gate structures formed across the fin structure in the core region and covering top and sidewall surfaces of the fin structure; a barrier structure formed in each peripheral region across the fin structure and covering top and sidewall surfaces of the fin structure; a plurality of source/drain regions formed in the fin structure between each barrier structure and a neighboring metal gate structure and between neighboring metal gate structures; and a first interlayer dielectric layer formed at least on the fin structure. The first interlayer dielectric layer covers sidewall surfaces of the metal gate structures and the barrier structures.

Abstract: A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

Abstract: This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

Abstract: The present technology relates to an image pickup device and an electronic apparatus that are configured to enhance characteristics. A solid-state image pickup device includes a photoelectric conversion section that is arranged on a semiconductor substrate and configured to photoelectrically convert an incident light, a moth-eye section that includes recesses and projections formed on a surface on a light incident side in the semiconductor substrate and has, when a cross section approximately parallel to a direction toward the photoelectric conversion section from the light incident side is viewed, a recessed portion protruding toward the side of the photoelectric conversion section, the recessed portion having a curvature or a polygonal shape, and a region that is arranged adjacent to and opposite to the photoelectric conversion section of the moth-eye section and has a refractive index different from a refractive index of the semiconductor substrate.

Abstract: A display device is provided. The display device includes a thin-film transistor substrate, a conductive pad disposed on the thin-film transistor substrate, and an adhesion film disposed on the conductive pad. The adhesion film includes a plurality of conductive particles. The display device also includes a light-emitting component disposed on the adhesion film. The light-emitting component includes a connection feature. The display device also includes a protection layer partially surrounding the light-emitting component. The connection feature of the light-emitting component has a lower portion not surrounded by the protection layer. The adhesion film has a thickness of T, one of the plurality of conductive particles has a diameter of d, the lower portion of the connection feature has a thickness of t, and 0<t?T?d.

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

Abstract: A microphone and its manufacturing method are presented. The manufacturing method includes providing a substrate; forming a ring opening extending from an upper surface of the substrate into the substrate; forming a ring separation component by forming a separation material in the ring opening; forming an insulation layer on the substrate; forming a front-end device on the insulation layer; and etching a back side of the substrate using the ring separation component and the insulation layer as an etch-stop layer to form a back-hole.

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.

Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.

Abstract: A thin film transistor array substrate includes: a first conductive layer including first lines for transmitting data signals to the thin film transistors; a second conductive layer disposed on the first conductive layer and including second lines for supplying a driving voltage to the thin film transistors; a first insulating layer disposed between a semiconductor layer and the first conductive layer and including a first material layer; a second insulating layer disposed between the first conductive layer and the second conductive layer and including a second material layer having a dielectric constant greater than that of the first material layer; and a contact plug penetrating the second insulating layer and the first insulating layer, and connecting the second conductive layer to the semiconductor layer. A taper angle of the contact plug in the second material layer is greater than that of the contact plug in the first material layer.

Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.

Abstract: A waterproof MEMS chip package structure includes a substrate having aa through hole cut through opposing top and bottom surface thereof, a waterproof membrane disposed in the through hole, an along chip bonded to the top surface of the substrate, a MEMS chip stacked on the analog chip and electrically connected to the substrate and the analog chip by wire bonding, and a top cover mounted on the substrate to form an accommodation chamber that accommodates the analog chip and the MEMS chip and communicates with the outside through the through hole. Therefore, the MEMS chip package structure of the present invention utilizes the waterproof membrane to block water vapor from entering the accommodation chamber through the through hole, thereby achieving the effect of protecting the chips.

Abstract: An opto-electronic device includes: (1) a subpixel region including: an electrode; an organic layer disposed over the electrode; and a conductive coating disposed over the organic layer; and (2) a light transmissive region including a nucleation inhibiting coating, wherein a surface of the nucleation inhibiting coating in the light transmissive region is substantially free of the conductive coating.

Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

Abstract: The present disclosure relates to a method of forming a deep trench capacitor. In some embodiments, the method may be performed by selectively etching a substrate to form a trench having serrated sidewalls defining a plurality of curved depressions. A dielectric material is formed within the trench. The dielectric material conformally lines the serrated sidewalls. A conductive material is deposited within the trench and is separated from the substrate by the dielectric material. The dielectric material is configured to act as a capacitor dielectric between a first electrode comprising the conductive material and a second electrode arranged within the substrate.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.

Abstract: Provided is a semiconductor light emitting device which includes: a light emitting structure including a plurality of semiconductor layers and configured to generate and emit light to an outside of the light emitting structure; a transparent electrode layer disposed on the light emitting structure; a transparent protective layer disposed on the transparent electrode layer; a distributed Bragg reflector (DBR) layer disposed on the transparent protective layer and covering at least a part of the transparent electrode layer; and at least one electrode pad connected to the transparent electrode layer through a hole or via.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A semiconductor package structure and manufacturing method thereof are provided, and the semiconductor package structure includes a semiconductor element, a top substrate, a bottom substrate, an insulating layer, and two metal conductive layers. The top substrate is mainly made of a conductive metal, and having a first separated portion on the top substrate, the first separated portion divides the top substrate into two blocks which are not electrically connected to each other. The bottom substrate is mainly made of the conductive metal, and having a second separated portion on the bottom substrate. The second separated portion divides the bottom substrate into two blocks which are not electrically connected to each other. The insulating layer is disposed between the top substrate and the bottom substrate. The metal conductive layer is disposed at two sides of the insulating layer and connected to the top substrate and the bottom substrate.