Patents Examined by Cuong Q Nguyen
  • Patent number: 10861953
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Patent number: 10862001
    Abstract: A display device and an electronics apparatus are provided. The display device comprises: a display substrate; and arrays of light-emitting elements on the display substrate, wherein the light-emitting elements include at least two types of electroluminescent quantum-dot LED, photoluminescent quantum-dot LED and micro-LED, wherein at least one type of the light-emitting elements is an electroluminescent quantum-dot LED, or at least two types of the light-emitting elements are micro-LED.
    Type: Grant
    Filed: October 8, 2016
    Date of Patent: December 8, 2020
    Assignee: GOERTEK. INC
    Inventors: Quanbo Zou, Denio Weng, Peixuan Chen, Xiangxu Feng
  • Patent number: 10862025
    Abstract: A magnetic memory device includes a first magnetic tunnel junction pattern on a substrate, a second magnetic tunnel junction pattern on the first magnetic tunnel junction pattern, and a conductive line between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern. The conductive line is configured such that a current flowing through the conductive line flows in parallel to an interface between the conductive line and each of the first and second magnetic tunnel junction patterns.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joonmyoung Lee, Ung Hwan Pi, Eunsun Noh, Yong Sung Park
  • Patent number: 10854690
    Abstract: A display apparatus includes a substrate including a display area and a sensor area, the sensor area including an auxiliary display area and a transmitting area, first display elements arranged over the display area, second display elements arranged over the auxiliary display area, transmitting units arranged in the transmitting area and configured to transmit at least a portion of light incident on the transmitting units, and an optical layer including a mesh pattern covering at least the second display elements.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Injun Bae, Donghwi Kim, Chulho Kim, Jin Jeon
  • Patent number: 10843917
    Abstract: A micromechanical device having a substrate wafer, a functional layer situated above it which has a mobile micromechanical structure, and a cap situated on top thereof, having a first cavity, which is formed at least by the substrate wafer and the cap and which includes the micromechanical structure. The micromechanical device has a fixed part and a mobile part, which are movably connected to each other with at least one spring element, and the first cavity is situated in the mobile part. Also described is a method for producing the micromechanical device.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: November 24, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Steffen Zunft, Bonsang Kim, Ando Feyh, Andrew Graham, Gary O'Brien, Michael Baus, Ralf Maier, Mariusz Koc
  • Patent number: 10847613
    Abstract: A semiconductor device is provided. The semiconductor device includes a mesa portion provided inside the semiconductor substrate and in contact with the gate trench portion, wherein the mesa portion has, at an end portion of an upper surface thereof, a shoulder portion in contact with the gate trench portion, the shoulder portion has an outwardly convex shape, the mesa portion has a first conductivity type emitter region that: is in contact with the gate trench portion and positioned between the upper surface of the semiconductor substrate and the drift region; and has a doping concentration higher than the drift region, a lower end of the emitter region at a position in contact with the gate trench portion is located at a deeper position in the depth direction than a lower end of the emitter region at a middle, in the transverse direction, of the mesa portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10840478
    Abstract: A display panel includes a substrate including an opening area and a display area surrounding the opening area, a plurality of display elements in the display area, and a groove arranged between the opening area and the display area, and including a first protruding tip and a second protruding tip having different heights from an upper surface of the substrate and spaced apart from each other, where the first protruding tip and the second protruding tip protrude from a side of the groove toward an inside of the groove.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seokkyu Han, Younggil Park, Kihyun Kim
  • Patent number: 10833128
    Abstract: There is provided a solid-state imaging device including a semiconductor base element, an organic photoelectric conversion layer formed above the semiconductor base element, a contact hole formed in an insulating layer on the semiconductor base element, a conductive layer formed in the contact hole and electrically connecting a photoelectric conversion part which includes the organic photoelectric conversion layer with the semiconductor base element, and a contact portion which is formed by self-alignment with the conductive layer in the contact hole in the semiconductor base element, and connected to the conductive layer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 10, 2020
    Assignee: SONY CORPORATION
    Inventors: Yuki Miyanami, Masashi Nakazawa
  • Patent number: 10832981
    Abstract: A display device including: a first substrate including a display area and a peripheral area; a display part disposed on the first substrate and to include a plurality of pixels; a second substrate disposed on the display part; and an inorganic layer disposed on the second substrate. The inorganic layer may include an opening, and the opening overlaps the display area and the peripheral area.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 10, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Jin Yang, Sung Hee Kim, In Ho Kim, Hyun Sik Park, Gyeong Nam Bang, Chun Gi You, Chang Ho Lee, Hye Yun Han
  • Patent number: 10830709
    Abstract: An interferometer uses a phase shift mask that includes an array of pixels that are aligned with a corresponding array of pixels of a detector. Each pixel in the phase shift mask is adapted to produce one of a number of predetermined phase shifts between a test beam and a reference beam. For example, the pixels may be linear polarizers or phase delay elements having one of the number of polarizer orientations or phase delays to produce the predetermined phase shifts between the test beam and the reference beam. The pixels in the phase shift mask are arranged in the array to include each of the predetermined phase shifts in repeating pixel groups in rows that are one column wide, columns that are one row high, or blocks of multiple rows and columns.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Onto Innovation Inc.
    Inventor: Nigel P. Smith
  • Patent number: 10818863
    Abstract: An organic electroluminescent element according to one embodiment of the disclosure includes, in order, an anode, an organic light-emitting layer, an electron transport layer, an intermediate layer, and a cathode. The electron transport layer includes a sodium fluoride layer. The intermediate layer includes an ytterbium layer. The ytterbium layer is in contact with the sodium fluoride layer on side of the cathode.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 27, 2020
    Assignee: JOLED INC.
    Inventor: Kosuke Mishima
  • Patent number: 10818745
    Abstract: An organic light-emitting display apparatus includes a substrate, pixels, a pixel defining layer (PDL), a first via layer, a second via layer, first lines, and a second line. The pixels are arranged on the substrate in a first direction (D1) and a second direction (D2) intersecting one another, and include organic light-emitting diodes (OLEDs). The OLEDs include pixel electrodes (PEs). The PDL covers edges of the PEs and defines light-emitting regions via openings partially exposing the PEs. The first and second via layers are between the PEs and the substrate. The first lines extend in the D2 between the first via layer and the substrate. The second line is between the second and first via layers. The second line at least partially extends around the light-emitting regions. The second line contacts the first lines through via holes. Each via hole is provided every two pixels arranged in the D2.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: October 27, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jisu Na, Youngjin Cho, Yangwan Kim, Joongsoo Moon, Keunsoo Lee
  • Patent number: 10818655
    Abstract: A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 27, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Guangsheng Zhang, Sen Zhang
  • Patent number: 10818740
    Abstract: An organic light-emitting diode (OLED) array substrate, a method for manufacturing an organic light-emitting diode (OLED) array substrate and a display apparatus are provided, and the OLED array substrate includes: a base substrate; a driving transistor, a first electrode, a second electrode, an organic material functional layer, and an auxiliary electrode connected to the second electrode disposed on the base substrate; and the driving transistor includes a gate electrode, a source electrode and a drain electrode, and the first electrode is electrically connected with the source electrode or the drain electrode; the auxiliary electrode is disposed in a same layer as at least one of the first electrode, the gate electrode, and the drain electrode.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: October 27, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yuxin Zhang
  • Patent number: 10811535
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 20, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10811480
    Abstract: An organic light emitting display (OLED) device includes a substrate, a semiconductor element on the substrate, a planarization layer on the semiconductor, and a light emitting structure on the planarization layer. The planarization layer includes a contact hole exposing a portion of the semiconductor and a plurality of grooves surrounding the contact hole. The light emitting structure is electrically connected to the semiconductor element via the contact hole.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eonjoo Lee, Jin-Whan Jung, Hyoeng-Ki Kim, Junhyuk Woo
  • Patent number: 10804397
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 13, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10804362
    Abstract: In a first aspect of a present inventive subject matter, a crystalline oxide semiconductor film includes a crystalline oxide semiconductor that contains a corundum structure as a major component, a dopant, and an electron mobility that is 30 cm2/Vs or more.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 13, 2020
    Assignee: FLOSFIA INC.
    Inventors: Rie Tokuda, Masaya Oda, Toshimi Hitora
  • Patent number: 10797211
    Abstract: A method of manufacturing support elements for lighting devices includes: providing an elongated, electrically non-conductive substrate with opposed surfaces, with an electrically-conductive layer extending along one of said opposed surfaces, etching said electrically-conductive layer to provide a set of electrically-conductive tracks extending along the non-conductive substrate with at least one portion of the non-conductive substrate left free by the set of electrically-conductive tracks, forming a network of electrically-conductive lines coupleable with at least one light radiation source at said portion of said non-conductive substrate left free by the electrically-conductive tracks. Said forming operation includes selectively removing e.g. via laser etching a further electrically-conductive layer provided on said non-conductive substrate, or printing electrically-conductive material onto the non-conductive substrate.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 6, 2020
    Assignee: OSRAM GMBH
    Inventors: Lorenzo Baldo, Alessio Griffoni, Federico Poggi
  • Patent number: 10796931
    Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin