Abstract: A power-residue calculating unit includes a K register connected to a first internal bus for once storing an intermediate calculation result to be discarded when a power-residue calculation is executed in accordance with a binary method. Therefore even when data to be discarded appears during the calculation, a write into K register is performed, so that current in a write operation flows thereby improving immunity against Power Analysis.

Abstract: Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The numerator and denominator are pre-scaled by the reciprocal. The denominator is decomposed to an equivalent expression that results in a number of leading insignificant values. Next, modifying a current remainder by forming a first product and subtracting the equivalent expression iteratively assembles a quotient.

Abstract: A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

Abstract: A system and method for accurately calculating a mathematical power function in an electronic device may include an application program that is configured to calculate a direct estimate of power function value for the mathematical power function during a direct linear interpolations procedure. The application program may also calculate an indirect estimate of power function value for a complement power function during an indirect linear interpolation procedure. The application program may then perform a final function-estimate calculation procedure to accurately produce a final estimated power function value from the foregoing direct estimate of power function value and indirect estimate of power function value.

Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.

Abstract: A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second adder adds an input carry from a previous digit to the first result and subtracts a value equal to the radix of the of the binary digits form the first result if the first result is greater than an initial threshold in order to generate an intermediate result. The system further includes a third adder for adding a second input carry from the previous digit to the intermediate result and subtracting the value of the radix from the intermediate result if the intermediate result is greater than a prescribed value such that the addition of the two binary digits are in redundant sign-digit format.

Abstract: A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discriminant. If a critical pattern is found in the discriminant, this indicates that standard rounding may give an incorrect result and further calculation is needed. The method can work for various rounding modes and types of floating point representations. The method can be implemented in a system as part of a processor instruction set or any combination of hardware, microcode, and software.

Abstract: A filter, in particular, a finite impulse response (FIR) filter having a variable data input and output rate is disclosed. The FIR filter includes a first-in first-out (FIFO) architectural buffer, an address generator for circularly generating respective addresses for FIFO of data items and providing the addresses to the buffer, a filter for performing filtering on data items having different rates, which are input from the buffer, and outputting one or more data, and a controller for controlling address generation of the address generator and controlling transfer paths of data items for filtering of the filter. It is possible to variably control the input and output rate of filtering data by the FIR filter.

Abstract: A method of decimal division in a superscalar processor comprising: obtaining a first operand and a second operand; establishing a dividend and a divisor from the first operand and the second operand; determining a quotient digit and a resulting partial remainder; based on multiple parallel/simultaneous subtractions of at least one of the divisor and a multiple of the divisor from the dividend, utilizing dataflow elements of multiple execution pipes of the superscalar processor.

Abstract: A random prime number is generated within a predetermined interval by precalculating and storing a single value that functions as a universal parameter for generating prime numbers of any desired size. The value, ?, is chosen as a product of k prime numbers. A number a is also chosen such that is co-prime with ?. Once the values for ? and a have been determined they can be stored and used for all subsequent iterations of the prime number generating algorithm. To generate a prime number, a random number x is chosen with uniform distribution, and a candidate prime number within the predetermined interval is calculated on the basis of the random number. This candidate is tested for primality, and returned as the result if it is prime. If the candidate is not prime, the random number x is multiplied by a, and used to generate a new candidate. This procedure is repeated, until the candidate is prime. Since a single value, namely ?, needs to be precalculated, economies of storage are achieved.

Abstract: Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

Abstract: One embodiment of the present invention provides a system that performs a carry-save square root operation that calculates an approximation of a square root, Q, of a radicand, R. The system calculates Q by iteratively selecting an operation to perform based on higher-order bits of a remainder, r, and then performs the operation. This operation can include subtracting two times a square root calculated thus far, q, and a coefficient, c, from r, and adding c to q. During this operation, the system maintains r in carry-save form, which eliminates the need for carry propagation while updating r, thereby speeding up the square root operation. Furthermore, the selection logic, which decides what operation to perform next, is simpler than previous square-root implementations, thereby providing a further speedup.

Abstract: An apparatus and method for reducing sequential bit correlation in a random number generator. The method includes generating a stream of random bits and selecting every Nth bit from the stream for accumulation and delivery to the requesting software application rather than delivering all the bits in the stream, where N is a programmable value. In one embodiment, the apparatus for carrying out the method includes a microprocessor that includes elements such as an arithmetic and logic unit, store unit, branching circuitry, and registers that execute instructions specified in microcode stored in a microcode memory. In another embodiment, the apparatus includes a plurality of multiplexers that select every Nth bit. In one embodiment, N is specified as an input parameter to a microprocessor instruction that stores the random bits selected.

Abstract: A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: A method and apparatus for quantum computing. A computer-program source code, data, and unsubstantiated output variables are converted into a class of computable functions by a program compiler. The computable functions are encoded, and a continualization method is applied to the encoded functions to determine a first-order, time-dependent, differential equation. Variational calculus is employed to construct a Lagrangian whose minimum geodesic is the solution for the first-order, time-dependent, differential equation. The Lagrangian is converted into a quantum, canonical, Hamiltonian operator which is realized as an excitation field via an excitation generator. The excitation field is repeatedly applied to a quantum processor consisting of a lattice of polymer nodes to generate an intensity-versus-vibrational-frequency spectrum of the lattice nodes.

Abstract: Provided is an adaptive filter that can reduce the computational complexity. The adaptive filter includes: a segmentation unit for segmenting N number of input signals into G number of signal groups; sub-filter unit having G number of sub-filters, which are corresponding to each of the signal groups, for filtering the corresponding signal group; an addition unit for summating the output signals of the sub-filter unit; an error computing unit for generating an error signal by comparing the output signals of the addition unit with a desired signal; filter coefficient updating unit having G number of filter coefficient updating units, each of which is corresponding to each of the sub-filters, for updating the filter coefficient of the corresponding sub-filter; and a switching unit for inputting the error signal to any one of the filter coefficient updaters optionally with respect to an iteration number k.

Abstract: A flexible Galois Field multiplier is provided which implements multiplication of two elements within a finite field defined by a degree and generator polynomial. One preferred embodiment provides a method for multiplying two elements of a finite field. According to the method, two input operands are mapped into a composite finite field, an initial KOA processing is performed upon the two operands in order to prepare the two operands for a multiplication in the ground field, the multiplication in the ground field is performed through the use of a triangular basis multiplier, and final KOA3 processing and optional modulo reduction processing is performed to produce the result. This design allows rapid redefinition of the degree and generator polynomial used for the ground field and the extension field.

Abstract: Herein disclosed is a digital filter coefficient setting apparatus which can search and select a specified filter coefficient element corresponding to a specified coefficient parameter inputted by a parameter inputting unit from among the plurality of filter coefficient elements stored in a coefficient storing unit and calculate a specified filter coefficient element on the basis of the specified coefficient parameter when the specified filter coefficient element is not selected from among the plurality of filter coefficient elements stored in the coefficient storing unit, thereby enabling to efficiently set a digital filter in response to a specified filter coefficient element corresponding to any possible specified coefficient parameter inputted therein, as well as to reduce a time required for obtaining the specified filter coefficient element.

Abstract: A method and a generator are described for high speed generation of an S-bit long pattern of a PRBS sequence to be periodically burst on to a bus of width S. The technique provides the calculation time being independent from the width S of the bus, and comprises calculation of all S bits of the PRBS pattern separately and in parallel by using previous PRBS patterns stored in a memory. For each bit to be generated, the generator performs a constant number N of logical operations require(by a polynomial defining the PRBS sequence.

Abstract: A portable lightweight combination laptop and pad computer has a display mounted on a main housing for movement between a closed position and an open position. In the closed position, a keyboard is covered by the undersurface of the display and the display viewing surface remains visible so that the computer may be used in the pad mode with a conductive stylus for data and command entry. In the open position, the keyboard is exposed so that the computer may be used in a laptop or desk top mode, or in a combined mode including the pad mode. The display is mounted to the housing by a four bar hinge mechanism, and a pair of latches are provided approximately mid-way between the front and rear portions of the housing along the side margins to securely latch the display in the closed position for storage, transit or use in the pad mode.