Patents Examined by D. R. Hudspeth
  • Patent number: 4651030
    Abstract: A decoder circuit for MOS memory of a redundant structure having shorter delays in access time contains a programmable element in a redundant circuit rather than connected in series on the word line driving signal.
    Type: Grant
    Filed: December 10, 1984
    Date of Patent: March 17, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshio Mimoto
  • Patent number: 4651033
    Abstract: A differential switching circuit includes a first current switching circuit having a first input terminal; a second current switching circuit having a second input terminal and a threshold different from that of the first circuit; and a constant current source commonly connected to the first and second circuits. Complementary input signals are applied to the first and second input terminals.
    Type: Grant
    Filed: January 27, 1984
    Date of Patent: March 17, 1987
    Assignee: Fujitsu Limited
    Inventors: Nobuyuki Yasutake, Toshitaka Tsuda
  • Patent number: 4651333
    Abstract: A shift register comprising a plurality of memory cells serially coupled together along a signal bus. Each one of the plurality of memory cells comprises a first amplifier, fed by an input logic signal, for amplifying and inverting the logic state of the input logic signal. A first storage section is included for either enabling storage in the first storage section of an electric charge corresponding to the voltage level of the amplified and inverted input logic signal, or disabling storage in the first storage section of the electric charge, selectively in response to a first control signal. The stored electric charge is converted to an intermediate logic signal having a predetermined voltage level. Each memory cell additionally includes a second amplifier, fed by the intermediate logic signal, for amplifying and inverting the logic state of the intermediate logic signal.
    Type: Grant
    Filed: October 29, 1984
    Date of Patent: March 17, 1987
    Assignee: Raytheon Company
    Inventor: Arthur M. Cappon
  • Patent number: 4649292
    Abstract: A CMOS power on detection circuit is described which includes pairs of complementary MOS transistors being connected in series between two supply lines. Each pair of transistors includes a long and a short channel transistor. Biasing the transistors by the rising supply voltage and by the voltages on the nodes formed by the pairs respectively allows to reduce or to cut current consumption once the detection is performed.
    Type: Grant
    Filed: March 6, 1985
    Date of Patent: March 10, 1987
    Assignee: Motorola, Inc.
    Inventor: Andreas Rusznyak
  • Patent number: 4649298
    Abstract: A single chip, bipolar logic circuit receives input signals in a differential amplifier or comparator stage coupled, without saturation, by differential current mirrors to drive an output stage of the push-pull variety. Various circuit arrangement are included to keep other bipolar transistors out of their saturation operating regions, and master transistors of the current mirror are provided with trickle bias when in the operating state to hold them at turn-on threshold for fast response to changes in state of the digital signals.
    Type: Grant
    Filed: January 9, 1985
    Date of Patent: March 10, 1987
    Assignee: AT&T Bell Laboratories
    Inventor: Frank P. Tuhy, Jr.
  • Patent number: 4649299
    Abstract: An improved strobe line driver circuit is disclosed that generates a plurality of strobe signals in response to a corresponding plurality of enable signals and a first clock signal. The circuit includes a clock enable transistor that generates a second clock signal. The circuit also includes a plurality of transistor pairs coupled to the first and second clock signals. Each transistor pair receives one enable signal and generates a corresponding strobe signal.
    Type: Grant
    Filed: April 16, 1984
    Date of Patent: March 10, 1987
    Assignee: National Semiconductor Corporation
    Inventor: Roy K. Yamanouchi
  • Patent number: 4649294
    Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled between an input terminal and the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between the input terminal and the upper transistor for biasing the upper transistor. A circuit device is coupled between the output terminal and the upper transistor for increasing the output voltage swing.
    Type: Grant
    Filed: January 13, 1986
    Date of Patent: March 10, 1987
    Assignee: Motorola, Inc.
    Inventor: Kevin L. McLaughlin
  • Patent number: 4649295
    Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled to the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between an input terminal and both the upper transistor and the first MOS transistor circuit for providing a high impedance at the input and for biasing both the upper transistor and the first MOS transistor circuit, wherein the first circuit is biased with a larger voltage than the upper transistor for improving the switching speed of the output signal.
    Type: Grant
    Filed: January 13, 1986
    Date of Patent: March 10, 1987
    Assignee: Motorola, Inc.
    Inventors: Kevin L. McLaughlin, Walter C. Seelbach
  • Patent number: 4645951
    Abstract: A semiconductor integrated circuit is provided which combines an MOS internal logic circuit (C-MOS in the preferred embodiment) with input and output buffers which have pin-compatibility with ECL circuitry. An ECL-CMOS level-conversion input buffer circuit arranged for a C-MOS internal logic circuit has a pair of emitter-coupled transistors which are responsive to an input signal at an ECL level. Thus, the input buffer circuit operates at a high speed. A CMOS-ECL level-conversion output buffer circuit arranged for the C-MOS internal logic circuit has an amplifying transistor, which has its base responsive to the output signal of the C-MOS internal logic circuit, and an emitter-follower transistor which has its base responsive to the collector signal of said amplifying transistor for generating an output signal at an ECL level at its emitter. Thus, the output buffer circuit operates at a high speed.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: February 24, 1987
    Assignee: Hitachi, Ltd.
    Inventor: Akira Uragami
  • Patent number: 4645944
    Abstract: In a high speed latching circuit (C) for selectively receiving one or plural slowly changing input data signals and latching them at high speed, one or plural first CMOS FETs (31, 33, 35, 37) and one or plural second CMOS FETs (32, 34, 36, 38) of p-conductivity type are connected in series respectively to form one or plural series connections (31+32, 33+34, 35+36, 37+38), wherein selection signals are given to the gates of the first CMOS FETs, input data signals are given to the gates of the second CMOS FETs and a flip-flop (30+39+41) is driven by selected one of the series connections.
    Type: Grant
    Filed: September 4, 1984
    Date of Patent: February 24, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masaru Uya
  • Patent number: 4645953
    Abstract: A current source for powering programmable arrays which provides means of eliminating the current supplied to portions of the array which are unimportant to the boolean arithmetic equation which the programmable array is programmed to model. The circuit includes fusible links (33-1 through 33-M) between the current source and portions of the circuit which may be unnecessary. Also included is means of opening (13-1 through 13-M) the fusible links (33-1 through 33-M) which connect the current source with the elements of the programmable array which may be unnecessary, thereby saving the power used to generate the current which would have been wasted in driving the unnecessary portions of the programmable array.
    Type: Grant
    Filed: July 3, 1984
    Date of Patent: February 24, 1987
    Assignee: Monolithic Memories, Inc.
    Inventor: Sing Y. Wong
  • Patent number: 4642492
    Abstract: A clock buffer circuit for multiple phase complementary clocking signals that receives a plurality of corresponding enabling signals and generates a like plurality of clock signals in response thereto. Each clocking signal is generated by a buffer module including a resistor, a pull-up transistor and a pull-down transistor, which are connected in series between a positive power supply and ground, with the clocking signal being taken from the node between the pull-up and pull-down transistors. In each module, before the clocking signal shifts from a low state to a high, the pull-down transistor is on so that the clocking signal is at a low state. The pull-up transistor in each module is controlled by the corresponding enabling signal and is enabled to begin conducting at the time that the clocking signal is to shift to a high state.
    Type: Grant
    Filed: October 25, 1984
    Date of Patent: February 10, 1987
    Assignee: Digital Equipment Corporation
    Inventors: John C. Beck, Daniel W. Dobberpuhl
  • Patent number: 4642488
    Abstract: A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit is provided which accepts Transistor-Transistor Lock (TTL) input signal levels without generating any significant DC current path. A reference voltage circuit (1, FIG. 1) provides first and second reference voltages (V.sub.A and V.sub.B, FIG. 1) which are coupled to first and second stages, respectively, of the input buffer circuit (3, FIG. 1), and which are of predetermined magnitudes and scaled relative to each other to permit the P-channel devices of the input buffer circuit to turn off completely when the input to the circuit is "high", while allowing a successively higher output at each successive stage of the input buffer circuit. The reference circuit 1 is compensated for power supply and process window variations.
    Type: Grant
    Filed: September 3, 1985
    Date of Patent: February 10, 1987
    Assignee: Codex Corporation
    Inventor: Lanny L. Parker
  • Patent number: 4642487
    Abstract: A special interconnect circuit which connects adjacent configurable logic elements (CLEs) in a configurable logic array (CLA) without using the general interconnect structure of the CLA. In one embodiment, an array of CLEs is arranged in rows and columns and a special vertical lead circuit is provided which connects an output lead of a given CLE in a given column to a selected input lead of the CLE above it and below in the same column. Special horizontal lead circuits are provided which connect a given output lead of a given CLE to a selected adjacent input lead of the CLE in the same row.
    Type: Grant
    Filed: September 26, 1984
    Date of Patent: February 10, 1987
    Assignee: Xilinx, Inc.
    Inventor: William S. Carter
  • Patent number: 4642485
    Abstract: In a push-pull switching circuit, whose output transistors are controlled by complementary control signals, one of the gate electrodes which carries a "low" signal is kept just at the threshold voltage of the output transistor to be cut off by means of a transistor substantially identical to the output transistors, the gate electrode and the drain electrode of this transistor being interconnected. The junction of this gate and this drain is connected to the common of two cross-coupled transistors, which are connected by their drains to the gate electrodes of the respective output transistors.
    Type: Grant
    Filed: November 5, 1984
    Date of Patent: February 10, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Bernardus H. J. Cornelissen, Henricus E. J. Wulms
  • Patent number: 4641048
    Abstract: A propagation delay time controller comprises a phase locked ring oscillator and a bias signal generator for controlling the propagation delay time of logic elements on an integrated circuit. The logic elements are of a type in which propagation delay time is a function of an applied bias signal. The ring oscillator, comprising representative logic elements on the controlled integrated circuit, oscillates with a frequency dependent on the propagation delay time of the oscillator logic elements. The bias signal generator compares the oscillator output voltage with a known, pulsed reference signal and generates a bias signal proportional to the integral of the phase difference between the oscillator and reference signal pulses. The bias signal is applied to all logic elements in the ring oscillator and to all other logic elements on the integrated circuit to be controlled.
    Type: Grant
    Filed: August 24, 1984
    Date of Patent: February 3, 1987
    Assignee: Tektronix, Inc.
    Inventor: Ira G. Pollock
  • Patent number: 4641044
    Abstract: After detecting a leading edge of a stop control signal supplied from an external circuit, an oscillation output signal is cut off at an input side of a frequency divider in synchronism with the first leading edge of a clock signal generated from the frequency divider, thereby stopping the generation of clock signals. The stopping of the clock signal generating operation is released in such a manner that, immediately after a trailing edge of an external control signal is detected, an internal state of the frequency divider is initialized, and the oscillation output signal which has been cut off is supplied to the frequency divider again, thereby generating a proper clock signal.
    Type: Grant
    Filed: November 29, 1984
    Date of Patent: February 3, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hajime Shiraishi
  • Patent number: 4639622
    Abstract: A voltage boosting circuit combination for semiconductor memory word-lines having a charge/discharge circuit including a first pair of MOSFET's and connected to a first clock signal. An output lead is connected from the charge/discharge circuit to a word-line of a semiconductor memory. The first clock signal .PHI.A thereon is connected to the charge/discharge circuit for actuating the MOSFET's to produce a voltage change on the output lead from a first voltage level to a second voltage level. The circuit combination also includes a threshold voltage circuit having a second pair of MOSFET's, which is connected to a second clock signal .PHI.C for controlling the voltage level in the threshold voltage circuit. A lead is provided connecting the threshold voltage circuit to the charge/discharge circuit. The circuit combination further includes an output signal boosting circuit having a third pair of MOSFET's which is connected to a third clock signal .PHI.
    Type: Grant
    Filed: November 19, 1984
    Date of Patent: January 27, 1987
    Assignee: International Business Machines Corporation
    Inventors: John J. Goodwin, Nicky C. Lu
  • Patent number: 4638183
    Abstract: A selective true or complement storage latch is disclosed which includes a data input switch having an input node connecting to a binary bit input source, a control input for accepting a first or second control state, a first data output node which is selectively connected to the data input node when the control input is in the first state and a second data output node which is selectively connected to the data input node when the control input is in the second state. There is also a first inverting gate having an input connected to the first data output of the data input switch and an output connected to a first storage node. The second inverting gate has an input connected to the first storage node and an output connected to the second storage node, the input of the second inverting gate being connected to the second output of the data input switch, the output of the second inverting gate being connected to the input of the first inverting gate.
    Type: Grant
    Filed: September 20, 1984
    Date of Patent: January 20, 1987
    Assignee: International Business Machines Corporation
    Inventors: Dale A. Rickard, Glen H. Rudelis
  • Patent number: 4638188
    Abstract: A logic system preferably for gallium arsenide integrated circuits uses dynamic pulsed logic gates which switch on each clock pulse, with the logical state of an output or data line being indicated by the phase of the pulsed output, which may be shifted or modulated with respect to a reference. An individual logic gate has a first signal generator having a capacitor which is either charged up or discharged during a set-up phase of a clock cycle, depending upon applied input logic signals. During a second, transmit phase of the clock signal, the signal developed on the capacitor is output from the gate. A second signal generator is an inverting slave of the first, and outputs the inverse logic state during the succeeding set-up phase of the first generator. With each gate switching on every clock period, all switching noise appearing in the ground or power supplies is at or above the clock frequency and can simply be filtered out with small chip capacitors, providing improvement in noise immunity.
    Type: Grant
    Filed: August 27, 1984
    Date of Patent: January 20, 1987
    Assignee: Cray Research, Inc.
    Inventor: Seymour R. Cray