Abstract: A circuit for selecting one of a plurality of positive voltages when both can be applied to an integrated circuit. The circuit comprises a sensing apparatus for determining which of the plurality of voltages is the highest, apparatus for providing the highest voltage to the substrate and apparatus for applying the highest of the plurality of voltages to the substrate to insure protection and proper operation of the integrated circuit.

Abstract: A semi-conductor decoder circuit includes 2.sup.N-1 circuits each formed of transistors vertically arranged in N stages, with the transistors of 2.sup.N-1, 2.sup.N-2 . . . 2.sup.1, 2.sup.0 number being disposed sequentially from the output stage in N stages in a tree structure. The gate width of the transistor at each stage is expanded as a distance from the output stage is increased so as to prevent an increase in ON resistance of the circuit and also to achieve a high speed operation.

Abstract: An integrated circuit having the circuit construction wherein a plurality of each of input and output circuits are formed in such a manner as to form pairs and to correspond to a plurality of external connection pads, respectively, and are used selectively to replace the function of an internal circuit. A signal transmission path of an input circuit formed so as to correspond to an external connection pad to which an external input signal is applied at an input portion and at least part of a signal transmission path of an output circuit formed so as to correspond to the external connection pad are connected in series between the external connection pad and an input terminal of the internal circuit in order to use the signal transmission function of the output circuit as the function of the internal circuit.

Abstract: An STL or ISL logic circuit comprising a plurality of single-input, multiple-output logic gates is provided. Each of these gates has a current source and a transistor including a base, emitter and multiple Schottky diode-to-collector contacts. The bases of the logic gate transistors are tied together to minimize metal interconnect stripes when a fanout greater than that of one gate is needed. Current hogging is reduced by an ohmic collector contact with connects the collector of each transistor together.

Abstract: An input buffer circuit comprised of MOS transistors includes an input terminal for receiving a tri-state input signal capable of taking any one of three potential levels, such as V.sub.pp, V.sub.cc and V.sub.ss. The input buffer circuit also includes a first detecting circuit having a first threshold level located between V.sub.pp and V.sub.cc and a second detecting circuit having a second threshold level located between V.sub.cc and V.sub.ss. Also provided is a third detecting circuit connected to the first and second detecting circuits to determine the level of the input signal applied to the input terminal.

Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between an upper NPN and a lower PNP pair of push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A P-channel MOS transistor is coupled between a node and both the collector of the NPN transistor and a first supply voltage terminal for biasing the NPN transistor. An N-channel MOS transistor is coupled between the node and both the collector of the PNP transistor and a second supply voltage terminal for biasing the PNP transistor. The gates of the MOS devices are connected to an input terminal. The node is further coupled to the bases of the NPN and PNP transistors and is coupled to the output terminal by a transmission gate or a resistor for increasing the output voltage swing.

Abstract: A circuit comprises P-channel and N-channel field effect transistors. A conduction electrode, such as a drain, of one of the transistors is coupled to a conduction electrode of the other transistor. Means are provided for ensuring that the currents in the transistors when changing state, and hence the rise and fall times of an output signal of the transistors, are substantially equal. Preferably, the ensuring means comprises the channel length of the P-channel transistor being smaller than that of the N-channel device. Alternately, either the doping level or the width of the P-channel device can be greater than that of the N-channel device.

Abstract: A current interface has an impedance buffering circuit which maintains a very low input impedance at an input node, while producing currents to two current outputs which increase and decrease, respectively, with increases and decreases in the input current flow. In a preferred embodiment, the impedance buffering circuit is an operational amplifier which has been modified to provide access to the collector terminals of a complementary output transistor pair. The collector terminals are connected to current mirrors which are also connected to an output node of the interface circuit. The amplifier and current mirrors effectively buffer the input and reconstruct changes in the input current at the output node, while maintaining a very low input impedance at the input node. Compensation for errors introduced by the changes in base currents of the complementary output pair is provided by a matching pair of complementary transistors.

Abstract: A three-state logic circuit comprising a logic gate on a semiconductor chip which includes first and second conductors, respective resistors connected to the conductors, terminals for receiving input signals, and transistors for generating complementary output signals on the first and second conductors by passing respective currents through the resistors as a logical function of the input signals with the output signals having high and low voltage levels V.sub.H and V.sub.L ; a control circuit on the chip having a first terminal connected to the first conductor, a second terminal connected to the second conductor, and a control terminal for receiving a control signal; a switching circuit within the control circuit which responds to the control signal by passing identical control currents through the respective resistors and into the first and second terminals to thereby lower the voltage levels on both the first and second conductors by at least V.sub.H -V.sub.

Abstract: A voltage level detection circuit connected between first and second feed lines, including a first depletion-type metal insulator semiconductor (MIS) transistor connected between the first feed line and a common node and having a gate connected to the first feed line, a second depletion-type MIS transistor connected between the common node and the second feed line and having a gate connected to the second feed line, and a circuit connected to the common node for generating an output signal when a potential at the common node reaches a predetermined value. The voltage level detection circuit can include a third depletion-type MIS transistor having a drain connected to the drain of the first depletion-type MIS transistor, a source connected to the source of the first depletion-type MIS transistor, and a gate connected to the output terminal of the output signal generation circuit, to output a stabilized output signal at the output terminal of the output signal generation circuit.

Abstract: An improved driving circuit which can drive a large load at a high speed. The circuit comprises an input inverter receiving an input signal, a first buffer circuit, a capacitive feedback element coupled between an output of the first buffer circuit and the input inverter, and a second buffer circuit having an input terminal coupled to the output of the input buffer and an output terminal coupled to an input of the first buffer circuit.

Abstract: A logic gate for use as a fundamental building block in more complex digital circuitry. The logic gate has multiple wired-AND input circuits, each capable of accepting multiple inputs, and each connected to a single pull-up field-effect transistor (FET), and to a common power supply. The wired-AND input circuits are ORed together and their signals level-shifted by diodes, before application to a FET output circuit that has one gate terminal and multiple drain output terminals. To facilitate expansion of the logic, these output terminals are connectable, either singly or together with outputs from other similar gates, as inputs to similar gates. The logic gate of the invention has a very low parts count compared with other logic topologies for the same purpose, and has an extremely favorable propagation delay-power product.

Abstract: An integrated JK-flipflop circuit comprises two cross-coupled inverters formed by a transistor and a resistor element connected in series therewith. Additional logic elements connect inputs of the flipflop to the cross-coupled inverters. It is a goal to provide the flipflop circuit on the smallest possible semiconductor area. This is achieved since the transistors of the inverters are designed as hot electron transistors, whereby each of these transistors is combined with one of the additional logic elements provided as a field effect transistor to form a common component which assumes two transistor functions but only requires the area of one field effect transistor.

Abstract: A input/output port for use in a device such as a central processing unit includes a common input/output terminal which serves as an input terminal when the port is set in a data input mode and as an output terminal when the port is set in a data output mode. The common terminal is connected to the junction between a pair of transistors connected in series between a high voltage source and ground. Also provided is a third transistor having a lower capability or power than the pair of first and second transistors and connected between the high voltage source and the common terminal. During data output mode, the pair of first and second transistors is turned on and off in a complementary fashion in accordance with data to be output. During data input mode, the pair of first and second transistors is maintained turned off and the third transistor is set either turned off or turned on.

Abstract: An inverter for use in a binary counter comprises a flip-flop having first and second input/output nodes respectively applied with input signals of opposite polarities, a first field effect transistor having a source-drain path connected between the first input/output node and a third node and a gate connected to receive a control clock signal, and a capacitor connected to the third node so as to hold the potential on the first input/output node when the first transistor is turned on. Further, there is provided a switch circuit connected between a supply voltage and a ground and having a first input connected to the third node, a second input connected to receive an inversion control signal, and an output connected to the first input/output node. This switch circuit is responsive to the inversion control signal so as to bring its output to a voltage condition opposite to that held in the capacitor.

Abstract: A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN.

Abstract: A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.

Abstract: An ECL (Emitter Coupled Logic) circuit is provided which has an increased ability to drive a large capacitive load or to drive a large fan-out circuit, wherein the power consumption per gate is reduced. The output circuit of the ECL circuit is provided with an emitter follower transistor which has the current therethrough detected by a detecting transistor. A current control transistor is provided to quickly charge the load capacitance under the control of the detecting transistor, and thus, the voltage drop of the output signal is improved. One of the emitter follower transistor and the current transistor are always cut off when the other is in a conductive state, and therefore, the current running through the circuit is reduced.

Abstract: An integrated circuit device having a simplified bias supply circuit for supplying bias power sources for a plurality of circuit units or cell units. The integrated circuit device cmprises: a cell unit array having a plurality of cell units disposed in a central portion of a semiconductor chip; a first power supply line and a second power supply line; and one or more common bias generating portions disposed at the periphery of the cell unit array, each of the common bias generating portions generating a single common bias voltage which differs from the potential of the second power supply line by a constant value. Each of the cell units comprises one or more logic circuit cells such as ECL type logic circuits, and an inner bias circuit which receives the common bias voltage and which generates a first inner bias voltage and a second inner bias voltage that are supplied to the respective logic circuit cell.

Abstract: A high voltage signal producing circuit, such as a panel display driver, includes an input terminal receiving an input signal, a first signal processor receiving the input signal through a conductive line, a second signal processor receiving the input signal through a capacitor, at least one output stage in which P- and N-channel MOS output transistors are connected in series, one of the MOS output transistors receiving a signal from the first signal processor in response to the input signal and the other of the MOS output transistors receiving a signal from the second signal processor in response to the input signal, a high voltage power source energizing the output stage, a first low voltage power source energizing the first signal processor and a second low voltage power source energizing the second signal processor.