Abstract: It is well known that the base width of a transistor has a direct bearing on transistor speed and the punch-through voltage. A solution to the transistor speed versus break down (punch through) voltage problem is disclosed. Output transistors are serially connected between power supply rails along with associated transistor base driving circuitry. The circuit arrangement ensures that the supply voltage divides between the series connected output transistors and prevents excessive voltage from being applied to each output transistor.

Abstract: A storage element for use in a logic array including a flip-flop device and a complex logic circuit interconnected in such a way that the output of the complex logic circuit is an input to the flip-flop. A Toggle Flip-Flop Control (TFFC) signal, an invert control (INV) signal, and a clock (CLK) signal are also inputs to the complex logic circuit. The output of the flip-flop connects to an output pad, an internal direct feedback line which is one of the means by which the flip-flop is connected to the comples logic circuit, and an external feedback bus which leads back to an associated AND-OR array. The inptu to the complex logic circuit is generated by the standard AND-OR array which is programmable to some degree.

Abstract: The invention pertains to a logic circuit with threshold and built-in safety such that any change in the characteristics of its components produces a relative increase of the threshold value. It comprises a comparator (7) one input of which receives a reference d-c voltage (VR) whereas the other input is connected to the junction point of a first and a second resistance (1, 2). A first d-c voltage (V1) of low relative value is applied to the free terminal of the first resistance (1), and a second d-c voltage (V2) of high relative value is applied to the free terminal of the second resistance (2) by means of a third resistance (3). According to the invention, there is applied at the junction point (A) of the second and third resistances (2, 3) a third d-c voltage (V3) of intermediate relative value by means of a fourth resistance (4) in series with a chopping commutator (6).

Abstract: A digital logic bus termination module that is to be plugged into a TTL logic backplane bus and in which the module includes a TTL logic circuit chip package having multiple terminals including a reference terminal, input terminal and output terminal. The TTL logic circuit chip package comprises an input diode, preferably a Schottky diode connected to the input terminal thereof and forming a bus termination clamping means. The bus line is connected to the input terminal of the chip package while the bus reference line is coupled to the reference or ground terminal for the circuit chip package. The TTL logic circuit chip package has the output terminal thereof unconnected so that only the diode is in operative association with the bus. One or more resistors may also be used in parallel with the clamping diodes for impedance matching purposes.

Abstract: A CMOS output drive circuit has two field effect transistors (FETs) implemented with a CMOS process and characterized by parasitic bipolar transistors. The back-gates of the two transistors are tied together, such as by forming the devices in a common well, and the back-gate of the second FET is also connected to prevent its associated parasitic bipolar transistor from conducting. Quiescent loads are applied to the two FETs so that their voltages are comparable during low output loading, resulting in a drive circuit with high input impedance and high output voltage swing. The output terminal is taken from the first FET, the voltage of which becomes unbalanced from the second FET at relatively high output loads, turning on the parasitic bipolar transistor for the first FET. This gives the drive circuit a desirably high input impedance and low output impedance for heavy output loads.

Abstract: A single input/multiple output NOR gate employs a reference voltage source for establishing the operational level of a multiple output current logic driver transistor. As the reference voltage source, the forward base-emitter voltage V.sub.be of a second transistor is used. Coupled between the current logic driver transistor and the second transistor is a multiple emitter diode-connected input transistor. One of the emitters of the input transistor is coupled in the current flow path from the current logic driver transistor to a current control resistor that is coupled in parallel with the base-emitter junction of the reference transistor, while a second emitter of the input transistor is coupled to the collector-emitter current flow path of the second (reference) transistor.In the absence of the application of current to the input transistor, the voltage level at the input is effectively equal to the sum of the forward base-emitter voltage drops of the input and second transistors.

Abstract: A finite state machine suitable for MOS fabrication is described. The finite state machine includes a programmed logic array (PLA). The PLA AND plane includes logical inputs and state signal inputs. The state signal inputs are decoded binomially. The state signals are used to activate the AND plane loads, thereby avoiding the necessity of using either a constantly active pull-up or precharge/selective discharge circuitry technique.

Abstract: In a semiconductor device including a plurality of input signal pads (P.sub.0, . . . , P.sub.7); a plurality of emitter followers (Q.sub.01, . . . , Q.sub.71) are connected to the input signal pads (P.sub.0, . . . , P.sub.7); a plurality of input signal buffers (BUF.sub.0, . . . , BUF.sub.7) are connected to the emitter followers (Q.sub.01, . . . , Q.sub.71); and a plurality of constant current sources (I.sub.01, . . . , I.sub.71) are connected to the emitter followers (Q.sub.01, . . . , Q.sub.71). The emitter followers (Q.sub.01, . . . , Q.sub.71) are in proximity to the input signal pads (P.sub.0, . . . , P.sub.7), and the constant current sources (I.sub.0, . . . , I.sub.7) are in proximity to the emitter followers (Q.sub.01, . . . , Q.sub.71) . The current values of the constant current sources (I.sub.01, . . . , I.sub.71 ) are determined in accordance with the length of the corresponding connections between the emitter followers (Q.sub.01, . . . , Q.sub.71) and the input signal buffers (BUF.sub.0, . . .

Abstract: A logic circuit such as an emitter coupled logic includes a current switch section formed of transistors and resistors and comparing an input signal with a reference voltage and an output section formed of at least a transistor and a resistor and producing an output signal in response to the comparison result, the resistors in the current switch section being polycrystalline resistors, for example, having a negative temperature coefficient of resistance whose sign is opposite to that of the resistor, for example a diffused resistor, having a positive temperature coefficient in the output section.

Abstract: A bias generator circuit includes a first high voltage for biasing a N-well region and a second delayed and lower voltage biasing a source region of a P-channel field-effect transistor so as to increase latch-up immunity. The generator circuit includes a high voltage generator and a multiplier circuit responsive to a power supply voltage for generating a first voltage level for biasing the N-well region. A delay network is responsive to the first voltage for generating a delay voltage. A level detection circuit is responsive to the delay voltage and the power supply voltage for generating a control signal when the delayed voltage reaches a predetermined level. A control device is responsive to the control signal for generating a second voltage for biasing the source region of the P-channel field-effect transistor. The second voltage level is delayed and lower than the first voltage level so that the PN junction is reverse biased to increase latch-up immunity.

Abstract: A logic circuit comprises an input terminal receiving an input signal of input pulses; first and second stages of C-MOS circuit formed by a first MOS FET of one channel type formed in said semiconductor substrate of one conductivity type and a second MOS FET of other channel type formed in well region of other conductivity type formed in the semiconductor substrate, said first and second stages being connected in a cascade connection; a first power terminal applying a first power voltage to the semiconductor substrate; a second power terminal applying a second power voltage to the well region; and a pulse converter converting the input signal to a pulse signal having a reference voltage of the second power voltage and short width pulses of the first power voltage produced in synchronism with the input pulses.

Abstract: A multilevel differential logic gate circuit for generating a plurality of levels of logic includes a single constant current source having its one end connected to a ground potential. The current source has a relatively small voltage drop. A first differential amplifier formed of a pair of first and second transistors have their emitters coupled together and to the other end of the current source to define a first level of logic. A second differential amplifier formed of a pair of third and fourth transistors have their emitters coupled together and to the collector of the first transistor to define a second level of logic. A third differential amplifier formed of a pair of fifth and sixth transistors have their emitters coupled together and to the collector of the third transistor to define a third level of logic.

Abstract: A "dotted or" logic circuit comprising Current Controlled Gate (CCG) circuits is described. In accordance with the present invention, Schottky diodes are cross-coupled between the dotted CCG circuits. Specifically, a Schottky diode is connected between the base of the base-to-collector diode of one CCG circuit to the emitter of the input transistors of another CCG circuit and vice versa.

Abstract: A GaAs D-MESFET logic system having a low power delay product has a switching second and a voltage level shifting section. The voltage level shifting section consists of a chain of diodes and a pulldown transistor. The switching section consists of an array of D-MESFETs which acts to speed up operation of a coupling capacitor. The low power dissipation of known capacitor coupled D-MESFET logic is thus preserved, while reducing gate delay.

Abstract: A temperature compensation system for semiconductor logic gates where the temperature compensation is accomplished by two depletion mode FET's in electrical series relationship is disclosed. One of the FET's is adapted to operate in its triode region of operation and the other in its saturation region of operation.

Abstract: An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array.The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate in the forward direction by a plurality of input signals, and a plurality of Schottky barrier diodes provided between the collectors of the bipolar transistors and output signal lines. The NOR or OR gate array includes a plurality of other bipolar transistors which are driven to operate in the backward direction by a plurality of output signals from the NAND or AND gate array.

Abstract: An integrated circuit (IC) of the invention is provided with a plural sets of power supply and ground lines within a package of the IC. Circuit elements, e.g., output buffers in the IC are divided into plural groups and each buffer group is coupled to the corresponding set of the power supply and ground lines. Each set of the power supply and ground lines is provided with independent wirings so that the magnitude of current change in each wiring and the value of each wiring inductance become small.

Abstract: A generator circuit for producing a negative bias voltage on a substrate for a semiconductor device employs a multistage on-chip oscillator driving individul charge pump circuits for each stage. The oscillator may produce a frequency related to the value of the negative bias, using a feedback circuit. Each of the charge pump circuits includes a capacitor and an MOS diode coupled to the substrate and another diode coupled to the ground terminal of the supply.

Abstract: The present invention is a temperature compensating circuit adapted for use with a CMOS to ECL interfacing circuit which uses one normally unused ECL logic gate, formed on a chip of many ECL logic gates for generating the supply voltages for the level interfacing circuit such that the output voltage levels from the interfacing circuit will automatically track with the temperature experienced by the chips' ECL logic gates.

Abstract: Integrated circuitry including at least one electrically erasable electrically programmable latch circuit. The contents of each latch circuit can be altered by applying programming voltages to the same terminals of the integrated circuitry that are used for other functions during times of normal operation. Each latch circuit provides localized memory for controlling the configuration of the integrated circuitry during times of normal operation, rather than depending upon memory external to the integrated circuitry for controlling the configuration of the integrated circuitry.