Abstract: A bias generating circuit for reducing an external DC power supply voltage to a predetermined, lower, stable DC voltage used as a power source for internal logic circuits in a semiconductor IC chip includes an oscillator for converting the external DC voltage into a pulse signal, a smoothing circuit for converting a pulse signal into the lower DC voltage, and a control circuit interposed between the oscillator and the smoothing circuit for varying the pulse duration of the pulse signal from the oscillator to a changed pulse signal, and for regulating the lower DC voltage to a predetermined amplitude in response to the voltage variation in the lower DC voltage. The control circuit comprises a CMOS inverter, a CMOS buffer circuit for varying the pulse duration of the output signal of the CMOS inverter, and a voltage compensating circuit for controlling the transconductance of the CMOS inverter in response to the variation of the lower DC voltage.

Abstract: The invention involves an "AND" logic circuit with built-in safety comprising a first and a second input to which pulses can be applied, and respectively tied to the base of a first and a second transistor (1,2) each having a collector to which a reference voltage (5) is applied by means of a corresponding resistance (6,7), and comprising, in addition, a third transistor (3) having its base tied to ground by means of the secondary winding (15) of a transformer whose transforming ratio is less than unity, its collector tied to the positive terminal of the d.c. voltage supply by means of a resistance (13), and its emitter having the reference voltage (5) applied thereto. According to the invention, the first transistor (1) has its emitter tied by means of a first diode (8) and its collector tied by means of a capacitor (9) to ground, whereas the second transistor (2) has its emitter directly tied and its collector tied by means of a branch comprising a capacitor (10) and a second diode (11) in series to ground.

Abstract: A sense amplifier circuit for a CMOS DRAM or the like uses cross-coupled P-channel load transistors and cross-coupled N-channel driver transistors. Both of the P-channel transistors are in an N-well in the center of a symmetrical layout on the chip. Each N-channel transistor is split into two separate transistors, one on each side of the N-well, so that a balanced configuration is possible.

Abstract: A CMOS reset circuit has a reverse biased diode and a latch for latching a p-channel enhancement mode MOSFET on during the first part of the power-on cycle. The p-channel MOSFET is part of a voltage divider which also includes a resistor. When the voltage between p-channel MOSFET and resistor reach the threshold of an n-channel enhancement mode MOSFET, the p-channel MOSFET is switched off. Reset pulses are provided through one or two inverters by a load on the latch.

Abstract: A transistor arrangement for clamping the output node of a semiconductor memory, including an inverter to parallel with a transmission gate for producing a differential output signal.

Abstract: A low power, low output impedance, CMOS voltage reference with high source/sink current driving capability. A CMOS current mirror preamplifier includes matched transistor pairs having their W/L ratios scaled to reduce the level of current to the subthreshold region. A CMOS source follower output stage also has its transistors biased in the subthreshold region. Circuitry for protecting the preamplifier from the effects of supply voltage and output voltage bumps is also disclosed.

Abstract: A power-up reset circuit has a first circuit for sensing a source voltage potential and generating a reset signal at an output when the source voltage potential rises above a threshold level. An input of the sensing circuit is coupled to the source voltage potential to permit a voltage at the sensing circuit's input to follow the source voltage potential during an initial rise of the source voltage potential. The power-up reset circuit further has a second circuit for sensing the source voltage potential and generating a time delayed signal at an output when the source voltage potential rises above a predetermined level. A termination circuit has an input coupled to the output of the second circuit and generates a termination signal at an output coupled to the input of the first circuit to terminate the reset signal in response to the time delayed signal.

Abstract: A communications interface for transferring data from a first binary logic circuit to a second binary logic circuit by using a trinary logic transmission channel. The first set of binary logic signals is converted into a first set of binary control signals which, in turn, control trinary drivers connected to the transmission channel. The trinary drivers drive the transmission channel to one of three discrete voltage levels as opposed to one of two levels in binary systems. Trinary receivers are located on the second binary logic circuit and are connected to the trinary transmission channel. The receivers produce a second set of binary control signals which are translated into a second set of binary logic signals for use by the second binary logic circuit.

Abstract: A generator for producing a negative bias voltage on a semiconductor device employs an on-chip oscillator driving two charge pump circuits. The oscillator produces a frequency inversely related to the negative bias, using a feedback circuit, thus reducing standby current. Each of the charge pumps include a CMOS inverter for controlling the transistor that functions as a diode connection to the ground terminal, producing an efficient charge transfer and speeding up generation of the bias voltage. Both charge pumps are used during power-up so the bias is rapidly increased to the operating level, then one is turned off to reduce current drain. A shunt circuit prevents CMOS latch-up during power-UP by coupling the substrate node to ground, preventing forward bias of N+ source/drain regions with respect to P substrate.

Abstract: An improved ECL circuit in which reference voltages have been eliminated is provided. The base of the reference switching transistor which is usually connected to a reference voltage is instead connected to the emitter of an emitter follower transistor coupled to the input switching transistor. The need for a reference voltage is thus eliminated because the emitter of such emitter follower transistor, and thus the base of the reference switching transistor, will be at the opposite level of the input to the base of the input switching transistor.

Abstract: A multi-input logic circuit which operates in a push-pull manner is composed of first and second logic sections. The first logic section is coupled between an output terminal and a reference voltage source and composed of a plurality of enhancement field effect transistors receiving a plurality of first input signals. The second logic section is coupled between the output terminal and a power source and composed of a plurality of depletion field effect transistors receiving a plurality of second input signals complementary to the first logic signals.

Abstract: A logic circuit on a semiconductor chip having a decoding or a selecting function has at least two input transistors coupled in parallel between an output node and a reference point. Input signals are applied to the input transistors, and an output is derived from the output node. Instead of employing inverters to produce complement signals, a conductivity of one input transistor is made different from that of the other input transistors. The proposed logic circuit can decode or select a combination pattern of input signals without using a complement signal producing circuit. Therefore, the number of circuit elements and signal lines are decreased.

Abstract: A charge coupled device (CCD) amplifier is utilized for amplification of charge packets as small as 500 electrons into usable signals. Very little noise is injected into the signal. The charge amplifier consists of two connecting electrodes, one designated as the detector G.sub.1 and the other designated as the response G.sub.2, physically separated by any convenient distance on the same LSI chip surface on which an NMOS field effect transistor (FET) is attached. Also coupled to the FET is another electrode G.sub.3 designated as the amplifier gate. The charge amplifier structure is embedded in the silicon dioxide layer, with the detector response, and amplifier electrode being located some convenient distance above the silicon-silicon dioxide interface.

Abstract: A flip-flop stores input data on both the leading and trailing edges of a clock pulse. The flip-flop includes a data path responsive to the leading edge of a clock pulse and a second data path responsive to the trailing edge of a clock pulse, thereby allowing data to be stored on both the leading edge and the trailing edge of a clock pulse.

Abstract: An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for CML) using two levels of series gating and one current source in order to establish scan/set testability of such latch. An additional interconnected circuit of v transistors and w resistors (b=2, w-1 for ECL; v=1, w=0 for CML) further establishes either a reset or a set capability for such latch. The economical total scan/set testable latch of x transistors and y resistors (x=18, y=11 for ECL; x=11, y=3 for CML) exhibits an excellent delay-power product since a single current is selectively steered into one of four different paths, the remaining three of which paths are shut down. Use of but a single current source provides further economy of silicon implementation.

Abstract: A circuit for generating accurate timing pulses which includes a timer means, a reference and feedback amplifier means, a feedback difference amplifier means, a difference amplifier means and a pulse shaper means. The timer means includes a constant current source which is triggered on by the input waveform signal and produces current i.sub.c. Reference and feedback amplifier means generates a voltage V.sub.ref which is proportional to current i.sub.c. Thus, if i.sub.c is too high or too low, V.sub.ref will represent the error value. The d.c. reference signal V.sub.ref' is applied to the feedback difference amplifier means which is a typical dynamic detector circuit. Feedback difference amplifier circuit is triggered and changes state when the voltage of the constant current timing circuit (which is proportional to i.sub.c) equals the reference voltage V.sub.ref'. The output signal from feedback difference amplifier means is applied to the straightforward difference amplifier means for further amplification.

Abstract: An input circuit for an integrated circuit structure achieves high speed operation without being affected by deviation or offset caused by the manufacturing process. The input circuit is of the type having a first inverter receiving an input signal and a second inverter receiving an output signal of the first inverter. The channel length of a driver MISFET of the first inverter is larger than that of a driver MISFET of the second inverter.

Abstract: A trip point clamping circuit for maintaining the voltage level at a node of connection to a sense arrangement including an inverter within defined bounds at the trip point of the inverter, the clamping circuit including a reference voltage, a source of similar current levels, a switch for turning the clamping circuit on and off, and a transistor responsive to the voltage level at said node of connection.

Abstract: An improved ECL gate having faster output transition times without requiring additional current is provided. Two switching transistors have their emitter terminals connected to a first current source. A reference switching transistor has its base connected to a reference voltage and an input switching transistor has its base connected to an input terminal. An emitter follower transistor is coupled to each switching transistor. A second current source is connected to each of the emitter follower transistors by coupling circuitry which shunts current from one emitter follower to the other thereby increasing the transition speed of the outputs. In the preferred embodiment, the emitters of the current source transistors for the two outputs are coupled through a common resistance to ground. The collector of the inverting emitter-coupled transistor is coupled via a capacitor to the base of the current source transistor for the non-inverting output.

Abstract: A signal generator for generating mask signals includes a plurality of conductors 0 thru N respectively; each of the conductors is coupled through a respective resistive means to a first voltage bus; first, second, third, . . . groups of transistors of a first set respectively couple conductors 1 thru N, 2 thru N, 3 thru N, . . . N to a second voltage bus; first, second, third, . . . groups of transistors of a second set respectively couple conductors 0, 0 thru 1, 0 thru 2, . . . 0 thru N-1 to a second voltage bus; and decoders turn on the transistors of a selectable group of the first set and a selectable group of the second set in response to externally generated codes CD#1 and CD#2.