Patents Examined by Dale M. Shaw
  • Patent number: 5428553
    Abstract: A power signal processing system and method for protection of a power system has a signal input unit for receiving a signal representing a condition of a power system; a plurality of processing units cooperating to apply to the received signal a predetermined process including a series of predetermined different computations thereby producing a control signal for controlling operation of the power signal processing system. The respective processing units operate to perform the predetermined different computations, respectively. A control unit is provided for controlling transfer of data among the processing units so that the different computations are applied, successively, to the received signal thereby producing the control signal which is used to cause, for example, the issue of a cut-off command to a circuit breaker.
    Type: Grant
    Filed: February 20, 1990
    Date of Patent: June 27, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Chiba, Mitsuyasu Kido, Tadao Kawai
  • Patent number: 5388217
    Abstract: Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory.
    Type: Grant
    Filed: December 13, 1991
    Date of Patent: February 7, 1995
    Assignee: Cray Research, Inc.
    Inventors: Gary E. Benzschawel, Lonnie R. Heidtke, Steven S. Chen, Fredrich J. Simmons, George A. Spix
  • Patent number: 5384906
    Abstract: A method and apparatus for synchronizing a plurality of processors. Each processor runs off its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor.
    Type: Grant
    Filed: August 23, 1993
    Date of Patent: January 24, 1995
    Assignee: Tandem Computers Incorporated
    Inventor: Robert W. Horst
  • Patent number: 5379377
    Abstract: A display system for dynamically indicating the status of conditions of a physical system shows as background on a raster display unit, a sketch of the physical system with text indicating the status of the various conditions juxtaposed to the sketch. In the preferred embodiment, the text for each condition is placed adjacent the general area on the sketch to which the condition pertains. It is intended that this display system will be implemented on a general purpose computer system by executing software which converts the computer system into the display system.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: January 3, 1995
    Assignee: Honeywell Inc.
    Inventors: Anil K. Gowda, Jeffrey C. Randall
  • Patent number: 5377322
    Abstract: Several processors and several communication control units are connected to a transmission medium. Each communication control unit has one or more terminal devices connected to it, and so any terminal device can be coupled to any processor. Each processor includes a central processing unit, a memory, and a control manager. The memory stores first information regarding processing being done with a terminal device coupled to the processor and second information regarding the communication control units connected to each of the processors and regarding the terminal devices being serviced by the processor. The control manager manages the communication control units based on the stored information. Information about the connections between the processors and the communication control units is broadcast to all processors. If any processor is faulty, another processor can take over the processing being done by the faulty processor.
    Type: Grant
    Filed: July 17, 1990
    Date of Patent: December 27, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Ogura, Katsumi Kawano, Kinji Mori, Hirokazu Kasashima, Manabu Shinomoto, Yasuo Suzuki, Masayuki Orimo
  • Patent number: 5377311
    Abstract: Use of a single pass print data stream conversion process when sufficient memory is available to store all the page data to be printed and reversion to a double pass conversion when insufficient memory is available. Scanning of the input data stream, storing the page data, and downloading the resource data to the printer continues so long as sufficient memory to store the page data is available. If the available memory is filled before the entire page is scanned, the stored page data is discarded. The scanning continues to download the resource data but the page data is no longer stored. When the page has been completely scanned, the scanning is restarted at the beginning of the page, downloading the page data to the printer and discarding the resource data during the second scan.
    Type: Grant
    Filed: March 16, 1993
    Date of Patent: December 27, 1994
    Assignee: International Business Machines Corporation
    Inventors: James R. Carlock, Leonard C. Lahey, Michael G. Lotz, Arthur R. Roberts
  • Patent number: 5377321
    Abstract: An image forming apparatus such as copying apparatus or laser beam printer in which each section of the apparatus is controlled by using a fuzzy inference. The apparatus comprises: processors to form an image; a detector to detect at least one state amount regarding the control of the processors; an inference operation unit to infer a control amount which is used in the control of the processors on the basis of the state amount; and a correction circuit to correct the delay amount of the control system in the inference. The processors include at least one of the charging device, exposing device, developing device, copy transfer device, paper feeding device, conveying device, fixing device, and image forming mode setting device. A predetermined value is added to or subtracted from the value obtained by the fuzzy inference so as to suppress the influence by the delay amount of the control system.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: December 27, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tokuharu Kaneko, Tadashi Suzuki
  • Patent number: 5371856
    Abstract: A transfer data storage system is used in a control processing unit which receives a transfer data in which a plurality of kinds of data having arbitrary data lengths are allocated within each frame, extracts each data within the transfer data included in a predetermined number of frames by the kind of data, and successively stores the extracted data into a memory.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: December 6, 1994
    Assignee: Fujitsu Limited
    Inventors: Toyohiko Yoshino, Yuji Takahashi, Hideki Nagasaki
  • Patent number: 5371852
    Abstract: The present invention provides a method and apparatus for enabling a cluster of computers to appear as a single computer to host computers outside the cluster. A host computer communicates only with a gateway to access destination nodes and processes within the cluster. The gateway has at least one message switch which processes incoming and outgoing port type messages crossing the cluster boundary. This processing comprises examining certain information on the message headers and then changing some of this header information either to route an incoming message to the proper computer node, port and process or to make an outgoing message appear as if originated at the gateway node. The message switch uses a table to match incoming messages to a particular routing function which can be run to perform the changes necessary to correctly route different kinds of messages.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: December 6, 1994
    Assignee: International Business Machines Corporation
    Inventors: Clement R. Attanasio, Stephen E. Smith
  • Patent number: 5369751
    Abstract: A disk cache control unit disposed between an upper-rank processor and a disk unit, comprising a cache memory for holding a copy of data stored in the disk unit, at least one first interface controller which checks, in response to an input/output command requesting data to be read from the upper-rank processor, whether or not the data requested by the command is stored in the cache memory, and requests a head positioning of the disk unit when the data is not stored in the cache memory, and a second interface controller which indicates head positioning to the disk unit in response to a head positioning request, notifies the completion of the head positioning to the first interface controller in response to a notice of the completion of the head positioning, and which reads data from the disk unit and stores the data in the cache memory when a data transfer request did not come in a specified time period set to read data from the disk unit without a rotational delay after a notice of the head positioning head b
    Type: Grant
    Filed: June 21, 1991
    Date of Patent: November 29, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kosaku Kambayashi, Katsunori Nakamura, Takao Satoh, Yoshihiro Asaka, Teruo Nagasawa
  • Patent number: 5369744
    Abstract: In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: November 29, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Fukushima, Shigeru Matsuo, Shoji Yoshida, Tooru Komagawa
  • Patent number: 5367632
    Abstract: An implementation of a flexible memory controller for a graphics hardware system that supports flexible allocation of frame buffer resources. The buffer selection and steering to the channels of the modification logic are performed by a programmable controller. Furthermore, the controller is capable of performing pixel functions that require multiple frame buffer accesses per pixel. Still further, independent control is provided for read and write sequences. Also, separate control is provided for buffer selection and bus steering. This function is useful for controlling systems where the frame buffer resources are limited. The present invention allows for assigning various buffers alternate functions based on the application's requirements, and may vary on a per window basis.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: November 22, 1994
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Bowen, David C. Tannenbaum
  • Patent number: 5367628
    Abstract: A multi-window system in multi-window environment includes a CPU for executing an application program for a window system and an application program for a non-window system for producing a display using the whole display screen, a standard-resolution display hardware for the non-window system, a high-resolution display system for the window system, and a window display component for displaying a picture of the application program for the non-window system corresponding to the standard-resolution hardware in window. High-speed graphics display of an existing application program can be attained in the window. The entire display picture of the existing application program can be displayed in the window at one time and the application program can be operated without scrolling thereof.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: November 22, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Ote, Masataka Okayama, Makoto Sano, Masanori Hashio, Katsuya Takanashi, Jun Kitahara, Sunao Hirata
  • Patent number: 5367641
    Abstract: An integrated circuit ("IC") interfaces a piece of communications equipment to a MIL-STD-1553 bus in accordance with the MIL-STD-1553 interface standards and operates in the MIL-STD-1553 defined bus controller mode of operation. The IC implements a command block configuration of data storage locations in an external memory. The command block includes a plurality of words arranged contiguously, a first word indicative of one of a plurality of different opcodes that define operation of the IC. The command block words include a MIL-STD-1553 defined command to be transmitted on the bus by the IC. A plurality of command blocks are arranged contiguously in a minor frame format. In order to sequentially execute a plurality of minor frames at different frequencies, the IC contains an internal timer that controls execution time of each minor frame.
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: November 22, 1994
    Assignee: United Technologies Corporation
    Inventors: John W. Pressprich, Anthony F. Jordan, Timothy D. Hornback, Gregory S. Carr
  • Patent number: 5367637
    Abstract: A self-tuning and efficient computer method is disclosed for the management of virtual storage applicable to dedicated real-time computer systems. This method interposes a layer between the application and the real-time computer system to form a two-layered structure to meet an application's request for virtual storage (i.e. buffer request). The method adds a real-time system's slower allocation (second layer) to guarantee the creation of all other buffers during one real-time period. The self-tuning first layer is checked first to satisfy a buffer request, while the untuned second layer is entered to create a buffer when the first layer fails; either the request size is not yet tuned, or the pre-allocated buffers have run out. These entrances to the second layer provide a monitoring mechanism from which a new pre-allocation definition, based on the system usage history, is derived to tune the first layer at the next initialization time.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: November 22, 1994
    Assignee: International Business Machines Corporation
    Inventor: Shuang N. Wei
  • Patent number: 5361337
    Abstract: An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: November 1, 1994
    Assignee: Sun Microsystems, Inc.
    Inventor: Kenneth Okin
  • Patent number: 5361387
    Abstract: A computer video display acceleration system and method is disclosed for increasing the speed with which modifications can be made to video memory. This system and method uses a video buffer section in system memory with high priority access by a central processing unit which can use the buffer space to make changes rapidly in the stored video information. Once the changes are completed, the data stored in the buffer is written as a block of data to video memory without requiring additional video memory read cycles.
    Type: Grant
    Filed: October 9, 1990
    Date of Patent: November 1, 1994
    Assignee: Radius Inc.
    Inventors: Gregory M. Millar, Tung-Faing Ko, Nicolas N. Moss, Jon F. Hueras
  • Patent number: 5361388
    Abstract: A terminal identifier correspondence management table provides the management of logical terminal identifiers generated by a host computer and assigned to each logical terminal and corresponding terminal identifiers generated for each terminal by a distributed computer. A logical terminal identifier is assigned to each logical terminal and is used by an interactive processing unit operating on a host computer. A distributed computer assigns a terminal identifier to each terminal and adds a terminal identifier into each message received by the distributed computer from a terminal, and the host computer deletes the terminal identifier in each message received from the distributed computer. The host computer provides the pertinent message to the interactive processing unit as if it were received from the logical terminal indicated by the logical terminal identifier corresponding to the received terminal identifier.
    Type: Grant
    Filed: April 7, 1992
    Date of Patent: November 1, 1994
    Assignee: NEC Corporation
    Inventor: Toshimasa Kutsuna
  • Patent number: 5359714
    Abstract: A computer backplane data path which connects computer backplane modules in a backplane structure. A T-ring made up of T-sections form a ring-like topology, wherein one T-section initiates from each computer backplane module and passively connects other computer backplane modules. At the end of the backplane structure each T-section folds back to continue connecting previously unconnected modules in a continuous loop process, until all modules have been connected with the desired number of T-sections. A plurality of A-paths, one per computer backplane module, so that each connecting T-section of the T-ring forms an active-passive, unidirectional data ring.
    Type: Grant
    Filed: January 6, 1992
    Date of Patent: October 25, 1994
    Inventor: Nicolas Avaneas
  • Patent number: 5359727
    Abstract: In a clock generating apparatus or clock generator employing PLL (phase-locked loop) by controlling a VCO (voltage controlled oscillator) in response to an output obtained by phase-comparing a clock signal based on an output signal of the VCO with an externally applied timing signal, a range of an oscillating frequency of VCO is varied in accordance with a frequency variation in the timing signal. A clock generating apparatus is provided for each of plural information processing sections, so as to surely synchronize operations of data processings including data transfers between the respective sections. When a clock signal is distributed to each of the information processing sections, the clock signal outputted from the distributing circuit is phase-compared in order to control the VCO.
    Type: Grant
    Filed: March 2, 1990
    Date of Patent: October 25, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kozaburo Kurita, Tetsuo Nakano