Abstract: A disk drive control system using a disk controller enables a host processor system to issue a data read/write command to a disk controller before a disk drive is brought into an access-enable state. Since a pseudo-ready signal is fixed at the active level the host processor system issues the data read/write command to the disk controller. Once the data read/write command has been issued the host processor system can perform processes other than disk control.

Abstract: An electronic data storage memory performs logic operations on the data values existing in its storage cells to eliminate the number of necessary memory accesses during bitblts. The time in which a bitblt can be completed in an image processing system is prolonged because of the number of memory cycles performed during a "raster operation". Thus, to reduce the number of necessary memory cycles, simple logic operations are performed in image processor memory so that a raster operation may take place without having to read, for example, the destination operand from memory. Since a bitblt performs a raster operation on each pixel in the bitblt block, the reduction in memory access time is proportional to the size of the bitblt block.

Abstract: A topology-independent method and apparatus for avoiding continuous looping of transmission of cells and for allowing broadcast of cells in a network implementing Asynchronous Transfer Mode ("ATM") or similar networking architectures. The disclosed method and apparatus provides for "misusing" fields in a cell header in order to provide for information identifying a cell as a broadcast cell and to provide for "expiration information" in the cell header. More specifically, a first station stores data in a first area of a cell intended for transmission on the network, where the first area is defined by standards to store certain information (in particular, it is defined in the preferred embodiment to store virtual path identifier information, VPI). The information stored identifies the cell as a broadcast cell. In other words, the field is "misused" to store this information.

Abstract: A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.

Abstract: An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.

Abstract: This invention relates to a protocol implemented in a communication system for exchanging data and control messages between adapters to which are attached different users, and a shared memory subsystem comprising a depository storage, a manager of storage and a microprocessor. Such protocol enables the adapters to be the initiators of the transmission and reception of data by using the control lines that connect the manager of storage to all adapters in the same way as the data bus and the address bus. Moreover, the adapters slice the messages into data bursts to which are associated control words specifying the sizes, the owner and the position of the burst in the message. Consequently, those data bursts may be interleaved when transiting on the data bus without the intervention of the microprocessor for the routing, and they will be stored in or read from the depository storage according to the identification of the user in the control word.

Abstract: A method for rapidly transferring serial data in a two conductor busing arrangement in which one conductor is utilized to transfer data and the other conductor is utilized to transfer clock signals, and in which a plurality of components are connected to the two conductors, at least one of which is capable of acting as a bus master including the steps of providing clock signals on the clock conductor which are active on both edges, placing a special signal on the data conductor to indicate the start of an operation, placing address data on the data conductor to indicate an address on the data conductor, placing data on the data conductor to indicate the type of transfer to be made, acknowledging the receipt of the address by a component being addressed, transferring data on the data conductor, placing a special signal on the data conductor to indicate the end of the data transfer, transferring a signal indicating a parity count, and placing another special signal on the data conductor to indicate the end of t

Abstract: A store-and-forward architecture which stores and distributes information programs to subscribers includes: information warehouses which archive information programs and dispense information programs in segments to central offices in bursts; central offices which manage subscriber's requests for service and buffer segments of information programs for delivery to subscribers in real-time under the subscriber's interactive control; and customer premises equipment. The central offices employ CO buffers, and each CO buffer includes: processors, for administering internal buffer operations and processing subscribers requests based upon the service presentation script and a program presentation map; interfaces for providing external access; busses for internal transport; buffer storage for storing segments of information programs; and memory storage for storing the script and map.

Abstract: In a speech rate modification system and method, correlation functions between different segments of input speech signal are computed by a correlator (17), the amplitude of the input signal is controlled by two multipliers (19, 20) which multiply the input speech signal by an increasing window function and by a decreasing window function, or vice versa, respectively, produced by a window function generator (18), and then output signals of the multipliers (19, 20) are added to each other by an adder (21) at such a relative delay within one unitary segment (T) as to maximize the value of the correlation function, and the input voice signal and the output of the adder (21) are selected by a multiplier (22), to be issued as a rate-modified speech signal.

Abstract: An image memory controller having a first address signal generating unit generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generating unit generates a second address signal for refreshing the image memory and a third address signal generating unit generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second, and third address signals to the image memory.

Abstract: A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.

Abstract: An interface between a real-time data link and a digital computer system utilizes data buffers between the computer central data storage and the data link. An interface control processor is responsive to a Data Transfer Command set comprising a SEND, a GET, a SET-TAG and a TERMINATE command. The commands include a TAG parameter that is set by the SET-TAG command to group sequences of SEND and GET commands so that logical streams of data are continuously transmitted and received across the interface. The SEND command includes a RECEIVE parameter to initiate the transfer of received data from the data link to the buffers after all data associated with the SEND command has been transmitted. Data transmission and reception operations are terminated by a TERMINATE command with a TAG parameter matching the TAG parameters of the sequence of commands controlling the operations. The SEND, GET and SET-TAG commands are stacked in a command queue and applied sequentially to the control processor.

Abstract: A mass storage/retrieval module for controlling the storage and retrieval operations of massive amounts of data in peripheral devices such as tape, disk, optical, etc. provides for a buffer memory system in each of the interface control modules which permit simultaneous and concurrent writing to buffer storage and reading out of buffer storage through multiple ports for high rates of data transfer operations. Redundancy and high reliability is provided in that each module of the system has dual busses and live replacement units such that, upon failure, an alternate unit can carry the circuitry requirements until the failing unit has been replaced.

Abstract: An apparatus is provided for logarithmic subtraction that is suitable for general purpose computing using the sign logarithm number system. In the sign logarithm number system, a sign bit is concatenated to a fixed point approximation of the logarithm of the absolute value of the real number being represented. Multiplication and division are easy and fast because the only steps required are to add or subtract the logarithms and exclusive OR the sign bits. In the prior art, logarithmic arithmetic has been restricted to limited precision applications (8-16 bits), such as digital filtering, because of the problem of accurate, high speed subtraction. The present invention provides a new circuit for subtracting two numbers represented in logarithmic form which makes design of arithmetic units for larger word sizes (32 bits) practical. The subtraction circuit approximates log.sub.b .vertline.1-b.sup.z .vertline., where z is the difference of the logarithms being subtracted.

Abstract: A computer display system and method is disclosed which allows a display controller in the display system to use a block of system memory rather than a dedicated frame buffer for display modes that do not require the bandwidth or the memory size of a dedicated frame buffer. The display system of the present invention includes an optional dedicated frame buffer to allow the display controller to support display modes that require the performance of the dedicated frame buffer, while retaining the capability to use system memory as a frame buffer for display modes that would only partially use the dedicated frame buffer.

Abstract: The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.

Abstract: An improved computer system ring interconnection comprising a plurality of nodes each such node being associated with at least one of a plurality of computer system components; transmission apparatus connecting each of said nodes to a node which is a source of information and to a node which is a recipient of information; each of such nodes comprising apparatus for distributing information received from a node which is a source of information, apparatus for receiving information from and transferring information to the associated one of the system components, apparatus for relaying between the transmission apparatus information to be transferred through the node directed to other such nodes, apparatus for placing a voucher signal on the transmission apparatus in response to the receipt of information from the associated one of such components to indicate that the component has information to be transmitted to another system component, apparatus responsive to the receipt of a voucher signal for determining whe

Abstract: Circuitry for handshaking between a command state machine and write state machine is described. The handshaking circuitry, the command state machine and the write state machine are part of a non-volatile semiconductor memory device that includes a memory array. The command state machine receives commands from a user and communicates valid commands to the write state machine, which responds by performing automated program and erasure operations on the memory array, as appropriate. The command state machine identifies valid commands based upon signals generated by the handshaking circuitry. The handshaking circuitry includes three latches, an OR gate and a NAND gate. The serially coupled latches store an idle signal from the write state machine. The OR gate is coupled to outputs from the second and third of the serially coupled latches and generates a signal indicative of the whether the write state machine is idle.

Abstract: An ISA-compatible computer system includes an additional function key on its keyboard. The additional function key does not have a defined function for conventional ISA-standard computers. When a conventional alphanumeric key or function key is activated on the keyboard, the computer system is interrupted using IRQ1 and the key information is communicated to the computer system so that the computer system can respond in a conventional manner using a conventional keyboard interrupt handling routine. When the additional function key and an alphanumeric key are activated in combination, a second interrupt different from the IRQ1 interrupt is activated (e.g., IRQ15). The computer system responds to the second interrupt by inputting an identification of the activated alphanumeric key and performing a selected predetermined function in response thereto.

Abstract: A controllable configuration management (CFM) state machine user interface is disclosed for use in the physical layer controller of a station or concentrator capable or insertion into a data transmission network that is capable of operating substantially in accordance with the FDDI protocol. In one aspect of the invention, the physical layer controller includes a null configuration register, a join configuration register and a loop configuration register. The null configuration register is capable of storing information indicative of a desired configuration of the physical layer controller when the CFM state machine is in a null configuration. Similarly, the join and loop configuration register are capable of storing information indicative of desired configurations when the CFM state machine is in the join and loop configurations respectively.