Abstract: A centralized supervisory control system allowing a centralized supervisory control center exactly to grasp information about failures and other events occurring in a plurality of supervised apparatuses, the center being also notified of time-of-day indications corresponding to such occurrences. Each of the supervised apparatus turns its information into blocks for output to an intermediate control apparatus. The intermediate control apparatus continuously collects such status data from the supervised apparatuses and compares the data with the status data currently held in its memory. If the latest status data from a given supervised apparatus are found to contain a deviation from the old data, the latest data are stored in memory along with a time-of-day indication corresponding to the deviation. The latest status data and the time-of-day indication are sent to the centralized supervisory control center.

Abstract: A circuit and processing logic is used to test, configure, and control the operation of computer system resource addressing control signals. The programmable circuit of the present invention determines when, in an I/O access cycle, the resource addressing control (IOCHRDY) signal should be activated by an I/O mapped system resource. The present invention includes lost circuitry for determining whether a particular system resource operates best in a late IOCHRDY mode or an early IOCHRDY mode. The test logic will force the IOCHRDY signal to remain active for an extended period of time. By extending the deactivation time of the IOCHRDY signal far beyond the time at which the deactivation would normally occur, the responsiveness of a command strobe (IORD/IOWR) may be tested.

Abstract: For processing an input message signal into a processed message signal, an on-line computer system comprises a saving buffer for memorizing as a memorized message signal a received message signal supplied from a message receiving circuit for receiving the input message signal. A processing unit produces a first request signal to be supplied with the received message signal as a first supplied message signal and produces a second request signal to be supplied with the memorized message signal as a second supplied message signal while processing the first and the second supplied message signals into the processed message signal. The memorized message signal is erased from the saving buffer when the processing unit produces a normal end signal representing a normal end of processing. The memorized message signal may be erased from the saving buffer when the processing unit produces the first request signal.

Abstract: A data compression controller for processing data between a host system and at least one device is disclosed. The data compression controller comprises a compression coprocessor for converting data between first format and second format at a determined controller ratio. The compression has two buffers for storing data of the first and second formats. When data is to be compressed, the coprocessor receives data directly from the host system into the first buffer. The coprocessor reads the buffered data and compresses the data for output to the external device through the second buffer. A coprocessor interface is coupled to the coprocessor for monitoring the buffers to determine the state of the buffers and the coprocessor; for example, if the such that the data to be compressed flows smoothly and consistently through the coprocessor. The input/output (I/O) controller is coupled to the coprocessor and the device for transferring data between the second buffer and the device.

Abstract: A frame buffer operating in fast page access mode with improved performance for operations such as scrolling and moving which typically access different display memory rows. The present invention utilizes a row/bank interleaved scheme of multiple display memory banks in the frame buffer such that each display memory bank supports a different set of non-contiguous display rows thus increasing the odds of display memory access in-page hits and decreasing the odds of display memory access in-page misses.

Abstract: A method and apparatus for a circuit physically realizing a time domain boundary buffer circuit for capturing data signals transmitted on an asynchronous domain bus and transmitting the data signals to a synchronous domain is described. The circuit comprises a data ready circuit and a data buffer circuit. The data ready circuit comprises a first flip flop is coupled to an asynchronous input, a second flip-flop is coupled to the synchronous domain clock and the output of the first flip flop, and a third flip-flop is coupled to the synchronous domain clock and the output of the second flip-flop, the circuit having an output coupled to a circuit output terminal; the third flip flop for providing a synchronous output which reflects an event occurrence on the asynchronous input. Other embodiments are also described.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: In a system of multiple digital modules which is operated synchronously via common clock means, there is provided circuitry for halting each module at the same simultaneously clock-moment after sensing of a selected condition in any one of the digital modules.

Abstract: A method and apparatus for analyzing signal timing requirements in complex electronic systems. The invention accepts from the user a set of specifications that express timing constraints, and generates therefrom a set of self-consistent "dependences" that relate signal locations to one another in terms of the minimum or maximum time that must elapse between such locations. The invention also generates signal pattern information that establishes the states of the various signals involved at different relevant times, and can be used to produce a signal profile.

Abstract: An IC recording medium for executing data transmission/reception without contact with a reader/writer.

Abstract: A document processing system controls the printing of documents represented in page description language form. Documents are represented by a page description language which is structured so that definition and declaratory commands are positioned only at the beginning of each distinct document segment. Each document has prologue sections, which contain definition and declaratory commands, and content portions which contain the specific tokens or commands for defining specific images. The definition and declaratory commands in the prologue sections of the document are arranged in a hierarchical tree so that each definition and declaratory command has a scope corresponding to the portion of the hierarchical tree subtended by that command. A structure processor handles resource declaration and definitions, dictionary generation, context declarations and references to data external to the document.

Abstract: A graphic display processing apparatus which includes having a CPU, a VRAM and a display controller, a data operation unit, an access cycle generator, an address generator and a sequential transfer sequencer. The graphic display processing apparatus also includes a mask pattern generator, dot mask generator and data position transformer. In the graphic display processing apparatus block transfer and character drawing are performed at high speeds, thereby making a window system more practical and offering comfortable operational environment to the user.

Abstract: A display memory having a DRAM port and a serial port, a video controller including a host graphics controller having a bus port, a lookup table and a digital-to-analog converter for receiving lookup table data from the lookup table and converting it into signals reproducible by a display, the DRAM and serial ports being multiplexed to a combined bus, the combined bus being connected to the bus port of the graphics controller, the lookup table having an input for receiving data from the combined bus, apparatus for causing passage of serial data along the bus from the display memory in higher priority than any other data for provision of display data to the lookup table whereby the lookup table can provide the lookup table data to the digital-to-analog converter.

Abstract: This invention relates to circuitry for extending TTL signals from a computer to a remotely located monitor and keyboard and which uses a first signal conditioning circuit proximate the computer to generally reduce amplitude of the video signals and bias them to a selected potential, after which the signals are applied to discrete conductors of an extended cable. The cable, in three embodiments described herein, may be up to 250 feet, 400 feet, or 1,000 feet. A second signal conditioning circuit at the monitor and keyboard end of the cable receives the attenuated signals and utilizes a threshold or pair of thresholds to effect reconstruction of the video signals prior to inputting them to the monitor. Significantly, amplitude reduction or attenuation of the video signals generally reduces high frequency video noise appearing on the keyboard clock conductor of the cable, preventing keyboard errors.

Abstract: A method of controlling an image memory system wherein non-interlace image data is written into the odd field and the even field memories, and the contents written into the odd field and even field memories are respectively read out so as to be converted into interlace image data. Each line of the non-interlace image data is alternately written into the odd field and even field memories in units of a plurality of dots. If the plurality of dots include dots for the odd field and dots for the even field, the image data of the plurality of dots are simultaneously written into both the odd field memory and the even field memory. When reading the image data out from the odd field memory, the image data for the even field written into the odd field memory is invalidated. Similarly, when reading the image data out from the even field memory, the image data for the odd field written into the even field memory is invalidated.

Abstract: A portable electronic device includes a storing unit for storing different types of communication protocols, a priority order setting unit for setting a priority order for the different types of communication protocols stored in the storing unit, a selecting unit for selecting a predetermined communication protocol from the different types of communication protocols on the basis of the priority order set by the priority order setting unit, and a communicating unit for performing communication using the predetermined communication protocol selected by the selecting unit.

Abstract: A modularized Time Code Interface (TCI) used to time tag asynchronous eve. Input and output connectors provide modularity in that the TCI may be readily plugged into or removed from a system. The TCI utilizes programmable memory for storing time intervals that are used in producing time of day data associated with the occurrence of an asynchronous event.

Abstract: A parallel processing computer system having an improved architecture for communication of information between nodes. The computer system of the present invention comprises at least three nodes; each of the three nodes for processing information. Each of the nodes comprises a routing means for routing information between nodes. The routing means allow reservation of a route through the network of nodes. Messages may then be transmitted from an origin node to a destination node over the reserved route. Use of a route reservation system reduces requirements for buffering of information at intermediate nodes on a route, improves message passing latency and increases node-to-node bandwidth. The present invention teaches communication of messages between nodes in a synchronous manner.

Abstract: Encoder arrangement including the cascade connection of a data source (VSS), an encoder circuit (ENC) and a buffer circuit (BUFC) which is part of a preventive policing circuit (PPC) adapted to reduce the data output rate of said buffer circuit when said output rate does not satisfy a predetermined probability distribution function (CCCP/CR) of said output rate. The PPC at the end of each measurement interval measures this data output rate, determines the interval (BRI) to which the measured data output rate belongs and generates an alarm signal (AL). Via a gating arrangement (AG, GC) the alarm signal controls the connection of a clock signal (CLO/3) with a reduced output rate to the read-out input (RO) of the buffer circuit (BUFC) when for the measured interval the cell rate has to be decreased.

Abstract: The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.