Abstract: A graphics engine receives commands or items in high-level graphics, translates these items to primitive codes representing primitive graphics, converts the primitive codes to individual pixel codes and addresses associated therewith and stores the pixel codes in an image memory according to priority in the pixel code. When a new pixel code is received for storing, the stored pixel code in the storage location associated with the new pixel code is read. The stored priority of the stored pixel code is compared with a display priority of the new pixel code and the pixel code having the higher priority is selected for storing at the storage location. The pixel codes are read from the image memory and in a conventional manner are converted using a video look-up table to produce output to a display device. The conversion from primitive graphics to pixel codes includes the process of converting symbol codes into an array of pixels using a symbol font memory.

Abstract: In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. The address generator formulates addresses as a function of distance from the origin of the desired destination area in a destination memory to the requested position in the destination area. A plurality of context drawing commands is used to define a desired context in which drawing graphics commands operate. Different parts of the context are changeable/redefinable independently of the other parts. Graphics commands have a format of multiple fields having corresponding parameters arranged in order of common use of the parameter such that fields of less commonly used parameters are at an omittable end of the format. Raster drawing commands are delimited by a beginning and end indicator to form a drawing unit. For clip list processing, a drawing unit is stored as a single occurrence in the system command buffer.

Abstract: A method is presented which eliminates the extra steps by an application to call a graphics function. The method eliminates the intercepting layer or program between the application and the graphic functions. The method may call hardware and software graphics functions directly and thus requires fewer processing steps and thereby reduces the amount of work the host computer must perform. The method and apparatus enables copy image data into a computer screen window faster than a comparable image display system that intercepts every call that an application makes to a graphics function.The method and apparatus enables an application program to directly control the location of image data in memory. The present invention enables movement of image data within memory or out of memory to make room for higher priority images. These features enable an application program to move image data between memories for different displays so that an image can move between screens.

Abstract: A residue buffer, for temporary storage of portions of transmissions from a CPU to a graphics processor. Graphics commands are transmitted, in transmission units of uniform size, from a processor unit to an address generator, which processes the commands. The portion of the transmission unit not immediately usable by the graphics processor is stored in the residue buffer.

Abstract: A modified frame buffer and pixel variable read-modify-write method are described for a high performance computer graphics system. Pixel variables are initially classified as decision variables, intensity variables or decision/intensity variables. Only decision/intensity variables requiring a read-modify-write operation, are stored in dual interleaved DRAMs for improved bandwidth. Decision variables and intensity variables each utilize a single address/data bus per video RAM module in the frame buffer, while decision/intensity variables require dual address/data buses for accessing the interleaved memory banks. Enhanced bandwidth is obtained with a minimization of raster engine I/O requirements.

Abstract: A scalable visualization system includes a plurality of scalable tiles (10) that each comprise a display portion (18) and a processing portion (20). Each of the display portions (18) define a portion of a physical display space. Each of the processing sections defines a processing node in the parallel processing system. The parallel processing system operating on a single node or a plurality of nodes. A message fabric (36) is provided to connect CPU nodes (34) and each of the tiles (10) together. The tiles (10) are scaled by interconnecting them to form the desired display space with each of the display elements (18). As each tile (10) is added to the overall display space, an additional CPU node (34) is also added, such that not only is the display space scaled up from a physical coordinant standpoint, but the processing power is also scaled up. In addition, each of the CPU nodes (34) is operable to update an associated display list (28) that defines the parameters of the display element (18 ).

Abstract: A method and apparatus for polling a status register selectively delays the returning of status data in the status register. Prior to polling, a match register is loaded via a system bus with a desired status. Status data is presented to the system bus when the status data is the same as the desired status. The features of the invention also permit the masking of selective bits of the status register during the comparison of the status data with the desired status. A mode register selectively inhibits the delayed presentation, and a timer ensures that status data is presented to the system bus within a predetermined interval even if the status data is not the same as the desired status.

Abstract: A computer system for dynamically configuring device drivers of removable system resources. The computer system comprises a processor, a system memory and an interface for receiving removable system resources such as feature cards. Each feature card includes a card memory area comprising: 1) a full device driver portion, and 2) a stub device driver portion. Upon insertion of a card into the computer system, the device driver stub code image is read from the card memory area and transferred into an area of computer system memory. The device driver stub code is then executed by the processor of the computer system from computer system random access memory. Conversely, the full device driver code is not transferred to the computer system random access memory; rather, the full device driver is executed while still resident on the card. Upon execution, the device driver stub enables access to the full card resident device driver by allowing memory mapping to the full device driver.

Abstract: A printer/display control apparatus for processing documents represented in a structured hierarchical page description language. The documents are provided as a document data stream defined by a hierarchical structure having as a top level a "Pageset" of "Picture". Both the Pageset and the Picture consist of an optional Prologue or an optional Prologue and an optional Body. The Body of a Pageset consists of zero or more Pagesets or Pictures. The Body of Picture consists of zero or more Pictures or Tokensequence. Each Picture or Pageset has a "begin" and "end" used to define in a document data stream the beginning and end of the definitions that make up that entity. This invention provides an efficient method to process the "begin" and "end" of the document data stream.

Abstract: Combined indication signals of data block transfers are generated by a device which reduces the number of interrupts to a host processor. The reduction in the number of interrupts enhances host system performance during data block transfers. An embodiment of the device may be a network adapter comprising network interface logic for transferring a data frame between a network and a buffer memory and host interface logic for transferring a data frame between a buffer memory and a host system. The network adapter further includes threshold logic for generating an early receive indication signal when a portion of the data frame is received. Indication combination logic delays the generation of a transfer complete interrupt to slightly before the expected occurrence of the early receive indication. The host processor is able to service both the transfer complete indication and the early receive indication in a single interrupt service routine caused by the transfer complete indication.

Abstract: A computing element for use in an array in a neural network. Each computing element has K (K>1) input signal terminals, K input backpropagated signal terminals, K output backpropagated signal terminals and at least one output terminal. The input terminals of the computing element located in row i, column j of the array of computing elements receive a sequence of concurrent input signals on K parallel input lines representing a parallel input signal S.sub.ij having vector elements (s.sub.ij1, s.sub.ij2, s.sub.ij3, . . . , s.sub.ijk).sup.T. The K input backpropagated signal terminals are coupled to receive an m-dimensional (m<K) backpropagated signal vector characterized to provide a measure of the performance error of the computing element. The computing element comprises a weighting function means responsive to the concurrent input signal S.sub.ij for computing a K-dimensional weighting coefficient and a scalar activation signal u.sub.ij by computing a K-dimensional weighting-coefficient vector, W.sub.

Abstract: An apparatus for altering the operating clock frequency of a computer system comprises an input port, a plurality of output ports, and instructing means coupled together by a bus. Latching means and gating means are coupled to CPU and the output ports to control the clock signal received. The input port receives a change frequency signal. In response, the CPU executes the instructions from the instructing means to store the contents of the CPU's internal registers into memory. The CPU then generates a frequency select signal and a reset signal that resets itself. The latch means stores and outputs the frequency select signal to the gating means. The gating means uses the frequency select signal to output one of a plurality of different frequency clock signals received at its select input as the operating clock input of the CPU. The CPU thereafter operates under the newly gated clock signal. After the CPU reset is complete, the CPU reloads its internal registers with the information stored within the memory.

Abstract: VGA controller interface circuitry that allows the VGA controller to reduce the cycle time of a write to the controller below the default write cycle time, resulting in a significant improvement of the controller's performance. The controller interface circuitry uses a Zero Wait State control signal on the system bus to reduce the cycle time by overriding the default cycle time for a memory write, unless the /Ready signal is asserted by the controller.

Abstract: A linguistic coding system and keyboard therefor for the use of people unable to use their own voices is described. The coding system and associated keyboard are based on the sentence rather than the word, phoneme or letter. The keyboard is coupled to a computer which stores a plurality of plural word messages or sentences in the memory thereof for selective retrieval by the keyboard. The sentences retrieved from the keyboard are fed to a voice synthesizer which converts them through a loud speaker to audible spoken messages The keyboard utilizes polysemic symbols on the respective keys and by designating a selected one of the keys and its associated polysemic symbols a primary message theme key, selected recorded plural messages in the computer memory may be retrieved by actuating a combination of the designated primary message theme key and other keys to vary the context of the polysemic symbols.

Abstract: Method and apparatus in a communications controller to transfer data between a host computer and the controller. The communications controller includes a channel adapter (CA) and a central control unit (CCU) for controlling the operation of the CA. In response to a request from the CCU, the channel adapter transfers data between the host computer and the channel adapter to or from a linked list of buffers until all messages contained in the linked list have been transferred. Only after all messages in the present transmission have been transferred, the CA interrupts the CCU to signal completion. In a preferred embodiment, the channel adapter includes a microprocessor and a read-only-memory containing programmed instructions for controlling the microprocessor. Together, the microprocessor under control of the read-only-memory instructions form an apparatus for carrying out the method.

Abstract: A system for an object based notification system. The notification system is designed in a flexible manner to support change notification in an object-oriented operating system. The change notification includes a memory for storing connection information including notification routing information and connection registration information. The connection registration information is stored in a connection object of the object-oriented system and the notification system updates the connection object with registration information indicative of enablement or disablement of notification. Then, when a notification event is detected, the object-oriented operating system selectively notifies objects in the system based on the connection registration information stored in the connection object in the memory of the computer system.

Abstract: In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the origin of desired destination area in destination memory to the requested position in the destination area. A plurality of drawing graphics commands specify different raster drawing operations. A plurality of context graphics commands is used to define a desired context in which drawing graphics commands operate. The defined context includes destination location for resulting data, type and plane depth of graphics operations, foreground and/or background color of resulting data. Different parts of the context are changeable/redefinable independently of the other parts. The graphics commands have a format of multiple fields. Different fields specify different parameters.

Abstract: The data processing system includes processing nodes and a graphics display device for processing a graphics data stream. The data processing system partitions a graphics data stream into a data segments or work groups for processing by the processing nodes. Next, the data segments are distributed for processing to the processing nodes. In response to receiving a data segment at a processing node, the data segment is processed to produce a processed data segment. The processed data segments are recombined into a processed graphics data stream. This processed graphics data stream is coupled to the graphics display device.

Abstract: A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.

Abstract: Improved method and apparatus are provided for performing parallel and pipeline processing of data sequences. The apparatus includes a plurality of memory circuits and a plurality of data processors wherein each data processor is constructed for parallel and pipeline processing of data sequences. Address controllers are provided for routing data between the memory circuits and the pixel processors. The address controllers are capable of directly coupling any memory circuit to any pixel processor so that data may be simultaneously transferred from a plurality of memory circuits to a plurality of pixel processors. Further, the pixel processors are provided with processing elements for performing data processing on neighboring data words of a data sequence.