Abstract: A picture display apparatus capable of displaying fringed characters is provided with a latch circuit for latching a character code read from a display data RAM. The latch circuit is provided between the display data RAM and a character generator and used to receive and hold the character code read from the display data RAM once and to supply the character code thus held to the character generator. A write circuit writes the character code to a memory when the latch circuit is not so timed as to receive the character code from the memory.

Abstract: Disclosed is an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having hi-tonal, monochromatic, or color input and output devices.

Abstract: A replicated data processing method and apparatus for a distributed processing system are provided in which a plurality of processors are connected to one another through a common transmission line. The processors perform processes using replicated data produced by resources such as files replicated in respective processors. Any processor issues an access request and broadcasts the request to the common transmission line. User's program of the processor is initiated by a first-received data in response to the request, and checks matching between the first-received data of the replicated data and the subsequently received data to repeat a retry processing for the request until a mismatch is removed.

Abstract: A computer related system including a reduced instruction set computer (RISC) central processing unit for effectively processing a data bottleneck phenomenon due to a great deal of data on a bus occurring from the use of graphic processing and windows. The system comprises a RISC central processing unit having address, instruction and data buses, a memory device for storing and reading instructions and/or data, which is connected to RISC central processing unit via the buses, an image processor for processing information as a video signal so as to be displayed on a video display apparatus, which is connected to the address and data bus, and a network interface connected with the data bus and enabling information exchange between the system and an external host computer.

Abstract: A personal computer based, multimedia, data processing system includes a software solution to the problem of synchronizing two or more data streams which output data to two or more multimedia output devices. One stream is a master and each other stream is a slave. The master stream generates sync pulses that can be handled in two different synchronization methods, master-slave independent synchronization or master-driven slave synchronization. Sync pulses are generated with a predetermined granularity, and synchronization is achieved when a slave stream is out of tolerance. Adaptive resynchronization may be used to speed up or slow down a slave stream.

Abstract: A device for interconnecting source users and destination users includes a common bus to which a memory with a plurality of independent buffers, a memory interface (22) and a central control apparatus (26) are connected. The memory interface (22) receives messages from source users, stores the messages in selected buffers and chains the buffers together. The central control apparatus generates inbound message queues and outbound message queues in response to commands which it receives from the memory interface.

Abstract: The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.

Abstract: A warning timer adapted for use in an interactive data processing system which generates an alarm when a user receives output at an input/output device when he or she is not likely to be paying attention to the input/output device. The user is assumed to be paying attention for a specified amount of time after he or she last sent a request to a computer or received a response from the computer. The specified amount of time corresponds to the length of the user's attention span. The warning timer operates as follows. When the user receives a response, it calculates the amount of time that has elapsed since the user last sent a request or received a response. If the elapsed time exceeds the specified amount of time, it generates an alarm to alert the user.

Abstract: An object interface is disclosed that supports three modes of inter-object communication--message processing (store and forward), conversational communication, and remote procedure call. A service broker manages service requests from, and responsive services provided by, a plurality of clients and servers, respectively, which may reside on different hardware platforms and operating systems and may be connected to computer networks having different network architectures and associated communications protocols. The broker manages the service offerings from servers and service requests from clients, and clients and servers communicate and exchange information with one another via the broker. The service broker includes different application programming interfaces for allowing participants to access the functionality of the service broker.

Abstract: A graphics processor that implements general purpose graphics processing and concurrent DMA display list processing to provide rapid response to display tasks. It is implemented with multiple channels of FIFO input circuits and with task interrupt and context switching circuits. Concurrent with a host processor that constructs and downloads a display list, the graphics processor processes display list instructions as they are downloaded. This reduces latency of the displayed image and facilitates more efficient use of the graphics processor. Implementation of multi-level nested interrupts and nested subroutines by means of interrupt and subroutine circuits further enhances graphics processing capability and enhances response times. Implementation of multiple channels with context switching enhances response times by permitting a higher priority task to interrupt a lower priority task.

Abstract: A host interface comprising a reassembler for reassembling and decrypting data that has been encrypted in accordance with a pre-defined key and segmented into a plurality of asynchronous transfer mode (ATM) cells. Each cell comprises a virtual channel identifier (VCI), a multiplexing identifier (MID) if the data is transmitted using the CCITT specified Class 4 connectionless transfer ATM adaptation layer (AAL), and a cell body.

Abstract: A graphics system is disclosed within which video graphics images are calculated via a computer and output for storage via a buffer whereby the image can be compressed/expanded for storage in compressed form in a dedicated semiconductor memory. The system also permits storage of compressed images on hard disk by directly connecting the compressed image store to a system bus. The compressed image store can be duplicated and further compression/expansion units added to broaden system versatility. Alternatively, a single compression/expansion unit can be used.

Abstract: In a computer system or process, sync point managers are distributed throughout each real machine for a plurality of execution environments, but all of the execution environments and sync point managers within one real machine share a common recovery facility and recovery log. A common recovery log is used by the recovery facility for all of the execution environments in the system. Different systems are interconnected by a communication facility and each has its own recovery facility and recovery log. A protected conversation can be initiated between the first and second execution environments in the same real machine, and the sync point managers within the respective execution environments coordinate the two-phase commit procedures associated with the protected conversations. A conversation manager within each real machine assists in routing the conversation between the first and second execution environments.

Abstract: A magnetic recording control apparatus includes conventional magnetic recording media, a large capacity type magnetic recording medium having a memory capacity corresponding to the sum of the capacities of a plurality of conventional magnetic recording media, recording unit for recording data of a plurality of conventional magnetic recording media to the large capacity type magnetic recording medium using a virtual volume corresponding to the recording capacity of one conventional magnetic recording medium and control data relating to the virtual volume as one recording unit, and/or division unit for dividing a data buffer for temporarily storing the data of the large capacity type magnetic recording medium into logical devices corresponding to the conventional magnetic recording media.

Abstract: A hardware mechanism capable of performing state saving and restoring operations, for use in a computer environment having a computer system having a central processor unit (CPU) with one or more data buses, a set of general purpose registers, instruction decoding logic and a mechanism for detecting interrupt conditions. The present invention generates new SAVE and RESTORE control signals and additional memory elements temporarily store the contents of the general purpose registers during interrupt conditions. The hardware mechanism includes an input section for transferring information from the one or more data buses to general purpose registers for storing the information. An output section is used for transferring the stored information from the general purpose registers to the data bus(es).

Abstract: A method and system for processing a graphics data stream in a computer graphics system having a parallel processing system. The graphics data stream includes a plurality of elements. The method and system of the present invention involve associating tags with elements in a graphics data stream, wherein each tag indicates a display order for the element associated with the tag. The elements are processed within a parallel processing system to produce processed elements, wherein each of the processed elements maintains an association with a tag. The processed elements are rasterized in a selected sequence to determine new pixel data sets, wherein rasterization of each processed element results in a new pixel data set for each of a plurality of pixels. Each new pixel data set includes order data derived from a tag associated with each of the processed elements.

Abstract: An apparatus which receives locking signals from a first device and provides a lengthened version of certain of these signals to a second device. The apparatus stretches the locking signal provided to ensure that the signal remains valid throughout the entire locked sequence. The apparatus also indicates when arbitration windows are available between back-to-back locked cycles, i.e. when it is okay to relinquish control of the host bus to a requesting bus master or device. The apparatus monitors cache controller activity and notifies arbitration logic when the last write cycle of a read-modify-write sequence or multiple transfer write cycle begins. When the cycle completes, the arbitration logic releases the bus, thus providing an arbitration window for other requesting bus masters and devices. In this manner, overlock conditions which block bus masters from obtaining control of the bus are prevented from occurring.

Abstract: A microprocessor system includes a processor unit, one or more subsystem adapter units, optional I/O devices which may attach to the adapters, and a bus interface. Memory in the processor and memory in the adapters are used by the system as a shared memory which is configured as a distributed First In First Out (FIFO) circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing self-describing control elements on the pipe which represent requests, replies, and status information. The units send and receive self-describing control elements independent of the other units which allows free flowing asynchronous delivery of control information and data between units. The distributed, shares memory can be organized as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements and the other pipe for inbound control elements. The control elements have standard fixed header fields with variable fields following the fixed header.

Abstract: An apparatus for controlling printing or display of documents represented in a structured hierarchal page description language. Documents are provided as a document data stream which can include references to external references and external data declarations which can be incorporated into the document by the content processor. Documents are defined by a prologue section which may contain definitions and declaratory commands, with content portions containing specific tokens or command for specific images. The document data stream has a hierarchal structure. A means to provide external declarations is provided which will process external declarations as if the external declaration which can be stored on a separate device were part of the original document data structure. The storage of the references to the external declarations is accomplished in a tree linked stack structure with a last in first out arrangement which allows for a faster search order of external declarations.

Abstract: An asynchronous memory controller comprises plurality of flip-flops connected in a series. The input of the first flip-flop receives a signal indicating the start of a bus cycle. The input of each succeeding flip-flop in the series is connected to the output of the preceding flip-flop. The odd-numbered flip-flops in the series are activated by a first state of a clock pulse; the even-numbered flip-flops in the series are activated by a second state of a clock pulse. Each flip-flop responds to a level of the clock pulse rather than a rising or falling edge.