Abstract: A semiconductor memory device includes: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit configured to generate a line choice address signal by combining the first address signal and the repair address signal according to a determination as to whether the repair address signal is to be used; and a cell line decoding unit configured to select one of a normal cell region and a redundancy cell region according to the determination, and select one of a plurality of local cell lines provided in the selected cell region in response to the line choice address signal.

Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.

Abstract: A semiconductor memory device includes a plurality of chips, a data path that is physically shared by the plurality of chips, a data input/output pad, and a data output driver. The data output driver is configured to receive merged data that includes data merged from a set of chip data read from the plurality of chips, compare the merged data to first reference data in a test mode, compare the merged data to second reference data in a test mode, and based on the comparisons, apply an output voltage at a data input/output pad.

Abstract: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract: A flash memory system includes a first flash memory cell having a first floating gate, a first source region, and a first control gate. The first control gate is connected to a word line. The first flash memory cell includes a first oxide layer separating the first control gate from the first floating gate and a first drain region connecting to a first bit line. The flash memory system also includes a second flash memory cell having a second floating gate, a second source region, and a second control gate. The second control gate is connected to the word line. The second flash memory cell includes a second oxide layer separating the second control gate from the second floating gate and a second drain region connecting to a second bit line. A comparator processes a first and second input signals received from the respective first and second bit lines.

Abstract: Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.

Abstract: Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells.

Abstract: Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost a magnetic field generated by current flowing therein.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: An MRAM according to the present invention has a magnetoresistance element 1. The magnetoresistance element 1 has: a first magnetic layer 10 including a first region 11 whose magnetization direction is reversible; a second magnetic layer 30 whose magnetization direction is fixed parallel to a magnetization easy axis direction of the first region 11; and a non-magnetic layer 20 sandwiched between the first magnetic layer 10 and the second magnetic layer 30. A domain wall DW is formed at least one end of the first region 11 of the first magnetic layer 10. The second magnetic layer 30 is formed to overlap with the first region and the above-mentioned one end. At a time of data writing, a write current is applied between the first magnetic layer 10 and the second magnetic layer 30.

Abstract: A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the data bus in a first operation mode and supplying data from outside to the sense amplifier via the write amplifier, the data bus, and the transistors in a second operation mode, and a control circuit supplying an electric potential to gate electrodes of first transistors that establish the electrical connection depending on the address, wherein in a first operation mode, the control circuit supplies a first electric potential to the gate electrodes of the first transistors, so that the first transistors exhibit a first impedance value and in the second operation mode, the control circuit supplies a second electric potential to gate electrodes of the first transistors, so that th

Abstract: Various embodiments of the present invention provide for extended life operation of multi-bit memory cells. As an example, some embodiments of the present invention provide electronic systems that include a plurality of multi-bit memory cells, an encoding circuit and a decoding circuit. Each of the plurality of multi-bit memory cells is operable to hold at least two bits. The encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells. The encoded output may be selected to be either a single two bit output representing the two bits, or a series of two two bit outputs representing the two bits. The decoding circuit is operable to reverse the encoding applied by the encoding circuit.

Abstract: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.

Abstract: One example memory device includes a memory array, a sense amplifier, and a tracking circuit. The memory array is formed of a plurality of memory cells. The sense amplifier is for accessing the memory array. The tracking circuit is for tracking memory read current of the memory array. The tracking circuit comprises one or more columns of tracking cells. Each column is coupled to a corresponding bit line to provide a drive current on the bit line for triggering a memory read operation by the sense amplifier. At least one of the columns comprises two tracking cells connected in series to each other.

Abstract: A semiconductor storage device and control method are provided. The semiconductor storage device includes a storage unit including a plurality of storage elements specified by addresses and divided into a plurality of blocks each corresponding to a plurality of the addresses, a write address decoding circuit that decodes a write address specifying a block to write data, a write buffer provided in a write signal path to input write data including write address to the block specified by the write address and a write buffer control unit that disables a write buffer provided in the write signal path for inputting the write data to blocks other than a block including a write address decoded by the write address decoding circuit.

Abstract: A memory cell includes a control gate and a transistor having a gate, a source junction, and a drain junction. The gate is coupled to the control gate, and the source junction and the drain junction are asymmetrical. For example, a channel doping associated with the source junction may be different than a channel doping associated with the drain junction. The memory cell also includes a write line coupled to the control gate, a source line coupled to the source junction of the transistor, and a bit line coupled to the drain junction of the transistor. The control gate could represent a second transistor, where the gates of the transistors are coupled together to form a floating gate. The memory cell could be programmed to store a single-bit value or a multiple-bit value, such as by storing the appropriate charge on the floating gate.

Abstract: A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

Abstract: A level shifter including a level shifter module configured to i) receive an input signal, wherein the input signal varies between a first level and a second level, ii) receive a first voltage supply signal and a second voltage supply signal, and iii) generate a latch control signal based on the input signal and one of the first voltage supply signal and the second voltage supply signal. The level shifter further includes a latch module configured to i) receive the latch control signal, ii) receive the second voltage supply signal and a third voltage supply signal, and iii) generate an output signal based on the latch control signal and one of the second voltage supply signal and the third voltage supply signal.