Abstract: A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.

Abstract: Hierarchical coding architectures and schemes based on multistage concatenated codes are described. For instance, multiple encoder and decoder hierarchies may be implemented along with use of corresponding stages of concatenated codes. The coding scheme generally includes an inner coding scheme (e.g., a polar coding scheme, such as a hybrid polar code or Bose Chaudhuri and Hocquenghem (BCH) code), an outer coding scheme (e.g., a Reed-Solomon (RS) coding scheme), and one or more middle coding schemes. The inner coding scheme is based on a polarization transformation (e.g., polar codes with cyclic redundancy check (CRC) codes, polar codes with dynamic freezing codes, polarization-adjusted convolutional (PAC) codes, etc.) which allows for embedding parity data from an outer code inside a codeword along with the user data. The outer coding scheme has a similar concatenated structure (e.g., of an inner RS code with an outer RS code).

Abstract: In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Abstract: One example method includes receiving an IO request that specifies an operation to be performed concerning a data block, determining if a policy exists for a device that made the IO request, when a policy is determined to exist for the device, comparing the IO request to the policy, recording the IO request, and passing the IO request to a disk driver regardless of whether the IO request is determined to violate the policy or not.

Abstract: Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device receives data bits for storage. Based on the data bits, the memory device generates a codeword that includes the data bits, parity bits, and placeholder bits. The memory device balances the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device stores at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device is able to re-invert the appropriate packets to recover the original data bits.

Abstract: Devices, systems and methods for improving reliability and security of a memory system are described. An example method includes receiving a seed value and a data stream, generating, based on the seed and using a physical unclonable function (PUF) generator, a PUF data pattern, generating, based on the seed, a pseudo-random data pattern, performing a first logic operation on the PUF data pattern and the data stream to generate a result of the first logic operation as a first data sequence, and performing a second logic operation on the pseudo-random data pattern and a second data sequence that is based on the first data sequence to generate a result of the second logic operation as a third data sequence for storage on the memory system, wherein the PUF generator is selected at least in-part based on one or more physical characteristics of the memory system.

Abstract: Various embodiments set forth techniques for erasure coding of replicated data blocks. The techniques include receiving, by a pre-designated node, data associated with an erasure coded strip from a first node; receiving, by the pre-designated node, a replica for a first data block; saving the replica in an erasure coded strip; and in response to a trigger condition, replacing, by the pre-designated node, the replica and at least one replica of a second data block with an error correction block.

Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an Error Correction Code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.

Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.

Abstract: A memory which includes a downlink error correction circuit suitable for correcting an error in data transferred from a memory controller based on a downlink error correction code transferred from the memory controller to produce an error-corrected data so that when an uncorrectable error is detected in the downlink error correction circuit of the memory or when an uncorrectable error is detected in the memory error correction circuit of the memory, the information that there is an uncorrectable error may be transferred to the memory controller in the memory system by using an uncorrectable error signal and an error flag signal, thus, improving the reliability of the memory system.

Abstract: Instructions stored on a computer-readable medium include, in response to receiving a new message for transmission, generating a candidate message by attempting recovery of a previous message from the new message and recovery bits of the previous message. The instructions include, in response to an indicator indicating that the attempted recovery was successful, computing a delta between the new message and the candidate message and generating a delivery message based on the computed delta. The instructions include, in response to the indicator indicating that the attempted recovery was unsuccessful, generating the delivery message based on the new message exclusive of the computed delta. The instructions include calculating new recovery bits from the new message. The instructions include storing the new recovery bits as the recovery bits of the previous message. The instructions include transmitting the delivery message to a destination over a communications channel.

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: respectively performing a single-frame decoding on a plurality of first data frames read from a physical unit set, the physical unit set contains a plurality of first physical units in a rewritable non-volatile memory module; in response to an entire decoding result of the first data frames meeting a first condition, obtaining error evaluation information related to the physical unit set, and the error evaluation information reflects a bit error status of the physical unit set; obtaining reliability information according to the error evaluation information; and performing the single-frame decoding on a second data frame read from one of the first physical units according to the reliability information.

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). Problematic patterns in a block of input data are identified, and the problematic patterns are relocated from an initial location to an erasure region of the block to generate a modified block. The modified block is erasure encoded into an erasure codeword, at least part of the erasure codeword is stored in the NVSM.

Abstract: Techniques involve: writing, when a first disk for dirty page storage has a failure, a first target page description generated by a first node and associated with a first set of target dirty pages of the first node and a second set of target dirty pages of a second node to a first page description storage layer for the first node in a second disk; writing a second target page description generated by the second node and associated with the first set of target dirty pages and the second set of target dirty pages to a second page description storage layer for the second node in the second disk; and restoring, when the failure has been eliminated, the first set of target dirty pages and the second set of target dirty pages in the first disk based on at least one of the descriptions.

Abstract: Aspects of the disclosure are directed to a computation unit implementing a systolic array and configured for detecting errors while processing data on the systolic array. Checksum circuit in communication with a systolic array is configured to compute checksums and perform error detection while the systolic array processes input data. Instead of pre-generating checksums in input matrices, input matrices can be directly fed into the systolic array through the checksum circuit. On the output side, the checksum circuit can generate and compare checksums with checksums in an output matrix generated by the systolic array. Error checking the operations to generate the output matrix can be performed without delaying the operations of the systolic array, and without preprocessing the input matrices.

Abstract: To implement low-latency register error correction a register may be read as part of an instruction when that instruction is the currently executing instruction in a processor. A correctable error in data produced from reading the register can be detected. In response to detecting the correctable error, the currently executing instruction in the processor can be changed into a register update instruction that is executed to overwrite the data in the register with corrected data. Then, the original (e.g., unchanged) instruction can be rescheduled.

Abstract: A method for determining the integrity of navigation data of a control unit of an automotive vehicle, including the steps involving setting two counters to a value strictly above the maximum of the two counters, and, in a waking phase, calculating the fingerprints of the data written to the reset safe area, comparing the counters and determining the integrity of the data when the counters are the same.

Abstract: Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device receives data bits for storage. Based on the data bits, the memory device generates a codeword that includes the data bits, parity bits, and placeholder bits. The memory device balances the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device stores at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device is able to re-invert the appropriate packets to recover the original data bits.

Abstract: Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output data strobe (DQS) signal. Interamble compensation circuitry selectively filters out interamble states of the DQS signal to reduce provision of interamble signals to downstream components that use the DQS signal to identify data latching times.